NOTE, SAKC has been renamed SIE. So, some places SIE is referred to as SAKC.
 Interface between processor and FPGA
Following picture shows a typical architecture for communication between a processor (or CPU) and extern peripherals. In this architecture the processor acts as a master, only having control of address and control buses.
Each peripheral owns a unique (not shared with anyone else) address range and will be used for data exchange with the CPU; this assignation is named memory mapping. The memory mapping gives information about the assigned memory range to each peripheral, and the address decoder is responsible of its physical implementation. Each peripheral owns a signal which alarms it the processor has started a communication with it, this signal is named Chip Selec (CS); The address decoder activates those signals according to the previously defined memory map.
 Processor-Peripheral communication
When the processor needs a service from a specific peripheral, it must place into the address bus an address assigned to said peripheral, this will make the address decoder activate its enabling signal. In this moment the selected peripheral establish communication with the processor, if it performs a reading operation, it will activate the nRD signal and the peripheral will take control of the bus, only the selected peripheral must take bus control, any other peripheral must stay at high impedance state which equals to disconnect his data bus, given thus the relevance of assigning unique address to each peripheral, otherwise two or more peripherals could take bus control at the same time creating a short circuit which may originate physical damage to the platform. If the processor performs a writing operation, it will activate the nRW signal, placing into the data bus the information to be transmitted and the selected peripheral will read it.
 Communication Peripheral-Processor
As mentioned before, only the processor has control over control and address buses, so when a peripheral needs to communicate with the processor it must use one of those options:
1. Polling Modifying one of its internal registers, so when the processor reads its content realizes of changes; This method requires for the processor to poll it periodically, and its used frequently in operations with the serial port.
2. Interruptions Using a signal called Interruption ReQuest (IRQ). The processor has a IRQ signal which when activated alters the execution flow, jumping to a default memory address known as Interrupt Vector, in this memory address the Interrupt Service Routine (ISR`) should be called.
The processor has a single IRQ signal, so to attend every peripheral an extern peripheral is needed to control the generated IRQ signals. This "special" peripheral is called Programmable Interruption Controller (PIC) who's in charge of the following tasks:
- Enabling interruptions global or individually.
- Define priority levels for interruptions.
- Provide an interface for the processor.
When a peripheral needs to be attended by the processor it activates its IRQx signal which is processed by the PIC, who determines if it raises its request to the processor. If the signal is sent to the processor, this one checks PIC's state to determinate the interruption's source thus determining the IRQ. Once finalised this ISR the processor must send this state to the PIC.
Once again is the processor wich starts communication towards peripherals, IRQ signal only exists to force a change in the program's execution flow for the determined peripheral to be attended.
 Extern Memory Controller EMC
JZ4725 processor has a peripheral in charge of controlling extern memories, this controller allows to handle static, NOR, NAND and SDRAM memories. SIE uses the CS2 signal which belongs to the second pool of static memory and is activated (low active) whenever an address in between 0x1400|0000 to 0x17FF|FFFF is accessed. Next picture shows reading and writing cycles for this processor.
JZ4725 processor does not provide nRD nor nWR signals, so nRDWR and nWE1 must be used. To be able to use EMC's second pool it is needed to setup the SMCR2 (Static Memory Controller Register) for it to show the connected hardware. For the SIE it is needed to setup the interface as a 8-bit estatic memory (0xFFF7700).
In addition, EMC allows to configure Setup(TAS), Wait(TAW) and Hold(TAH) cycles. Those parameters insert clock cycles during the reading process which allos to optimally adapt any kind of memory with different access times (see previous picture).
Here you can find an example in user space which allows to configure EMC for SIE platform, this example will be deep explained in another section.
 Basic Processor Interface Architecture
Next picture shows blocks diagram and basic architecture implemented into SIE's FPGA. This architecture must be maintained to allow the communication between the processor and peripherals implemented into the FPGA.
In this picture we can observe the same architecture previously shown with the following modifications:
- Processor`s signals Address Data nCS2 we0_n are not in phase with clock signal from FPGA, so they must be synced with it; SYNC module is in charge of it.
- Tri-state buses can't be implemented inside FPGA, tri-state buffers can only be used in the FPGA's pins, so peropherals must have two input data buses (Orange color) and another for output (green color).
- It must be provided a circuit at peripherals output buses which allows the selected peripheral's information transfer. Represented as a Multiplexor in picture.
- Given that FPGA is way fastest than the processor, it is necessary to generate a pulse lasting a FPGA clock cycle for the we0_n write signal. This is done to avoid to perform more than one write operation. This task is done by the Write Pulse Generator module, which time diagram representing its operation is shown in picture.
- A tri-state buffer must control access to Data bus, this buffer must show an high impedance state when no peripheral is selected or when a write operation is being done and must allow the data transfer from the peripheral in read operations.
 Read Operation Equivalent Circuit
When the processor performs a read operation it sets the nCS2 signal into a low logic level and RDWR_n signal in high, so the function (~RDWR_n | nCS2) takes a 0 value, activating the tri-state buffer, connecting then the output data bus from the selected peripheral to the processor's data bus. Previous picture shows involved signals and blocks.
 Write Operation Equivalent Circuit
When the processor performs a write operation to a determined peripheral the tri-state buffer and any non selected peripheral are in a high-impedance state ((~RDWR_n (1) | nCS2 (0)) = 1) and disabled respectively, thus resulting circuit would be thw shown in the following picture.
 FPGA Implementation using Verilog
Here can be found an implementation example for this interface in Verilog.