EMC

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[edit] External Memory Controller(EMC)

General Description


The main feature of the External Memory Controller is the address virtualization of off-chip memories. It assigns an address range to execute the SDRAM, NAND Flash and STATIC MEMORIES like NOR flash, burst ROM or ROM. In that way, the controller has a number of registers for each access function and each one has the control signals to handle data and addresses from memories. The first graphic of this article shows a simple in, out and in/out distribution of signals which compose the controller operation.Each label describes both sets of signals as individual signals.These signals are necessary for exercise control over registers that has each interface and they in combination achieve the expected behavior of controller. the labels will be mentioned on each interface explanation.

General I/O description


Based on Jz4725 Multimedia Application Processor Programming Manual, the next table lists the EMC pins of our interest

Signal Pin Name Description
D31-D0 Data Bus Data I/O
A22 - AO Address Bus Address Output
CS4~1# Static chip select 4 ~ 1 Indicates the static bank being accessed
DCS# SDRAM chip select Indicates the SDRAM bank being accessed
CAS# Column address strobe SDRAM column address strobe signal
RAS# Row address strobe SDRAM row address strobe signal
RD/WR# Read/write Data bus direction designation signal and also used as SDRAM write enable signal
DQM0/ Byte enable 0 SDRAM D7–D0 selection signal
DQM1/ Byte enable 1 SDRAM D15–D8 selection signal
DQM2/ Byte enable 2 SDRAM D23–D16 selection signal
DQM3/ Byte enable 3 SDRAM, D31–D24 selection signal.
CKE SDRAM Clock enable Enable the SDRAM clock
Wait# / Wait External wait state request signal for memory-like devices
FRE# NAND flash read enable NAND flash read enable signal
FWE# NAND flash write enable NAND flash write enable signal
FRB# NAND flash ready/busy Indicates NAND flash is ready or busy

The next graphic shows the behavior block diagram of controller.

MEMORIES ACCESS BLOCK DIAGRAM

[edit] Static Memory Interface

Although we have no interest in this part of EMC, because is not used in SIE, is very important know its operation for future programming tasks. So we will explain the registers briefly in case that processor is used with NOR flash, SRAM or uses its internal memory.

The static memory interface has two registers for each bank: SMRC(STATIC MEMORY CONTROL REGISTER) and SACR(STATIC BANK ADDRESS CONFIGURATION REGISTER). In SMRC there are signals that control the time access data of memory and decisions are made regarding the characteristics of access; In the SACR we define the base address and the mask of static bank.

[edit] NAND Flash Interface

Both 8-bit or 16-bit NAND flash can be connected to static memory bank 4 ~ bank 1. The following table lists the NAND Flash Interface 32-bit Registers.

Register Description



Name Description Reset Value Address
NFCSR NAND flash control/status register 0x00000000 0x13010050
NFECCR NAND flash ECC control register 0x00000000 0x13010100
NFECC NAND flash ECC data register Undefined 0x13010104
NFPAR0 NAND flash RS Parity 0 register 0x00000000 0x13010108
NFPAR1 NAND flash RS Parity 1 register 0x00000000 0x1301010C
NFPAR2 NAND flash RS Parity 2 register 0x00000000 0x13010110
NFINTS NAND flash Interrupt Status register 0x00000000 0x13010114
NFINTE NAND flash Interrupt Enable register 0x00000000 0x13010118
NFERR0 NAND flash RS Error Report 0 register 0x00000000 0x1301011C
NFERR1 NAND flash RS Error Report 1 register 0x00000000 0x13010120
NFERR2 NAND flash RS Error Report 2 register 0x00000000 0x13010124
NFERR3 NAND flash RS Error Report 3 register 0x00000000 0x13010128


  • NFCSR is read/write register initialized by any reset that configures the NAND flash.
  • NFECCR is R/W register initialized by any reset that is used in the detection and correction of possible errors, for example when the content of the NAND Flash is copied to the SDRAM and is needed to check data validity (ECC). Also allows the selection between Hamming and RS codes algorithms for correction.
  • NFECC is the R only register that contains the result of ECC calculation.

The following registers are related with the RS Correction:

  • NFPARn (n=0,1,2) store the parity data during RS correction.
  • NFINTS stores the interrupt flag and error count information.
  • NFINTE enables or disables nand flash interrupt.
  • NFERR stores the index and error value for each error symbol after RS decoding.

[edit] NAND Flash Operation

In first place, when NFEn bit of the NFCSR is set, the NAND Flash is enabled to be accessed. Depending of the choice of bank, the partition of memory will be completed. Any address written will be overwritten in the new location belonging NAND Flash. The SMCR will configure the time to access the NAND flash but the choice of bank is controlled by NFCE and NFCSR. The signals that control direction connection are CS, FRE, FWE, FRB, A16 and A15. There are two codes that could be used for ECC generation:

  • Hamming, the parity consists of 24 bits per 512 bytes and 22 bits per 256 bytes.
  • Reed-Solomn, or RS controller, uses a code with 511 symbols of 9 bits, in which the registers NFPAR0-2 and NFERR0-3 are used for parity data and generation of error information, respectivily.

[edit] SDRAM interface

Like was showed in the previous section, this section has many registers too. SDRAM is used like RAM of our system, and the processor supports 16-bit or 32-bit wide SDRAM. Unlike the two previous interfaces, SDRAM has its own banks like was showed in the second graphic of this document. The signals that are included by this interface are DCS,DQM3-0, A14-A0, RD/WR,CAS, RAS, CKE and CKO. The table below shows the register description:

Name Description Reset Value Address
DMCR DRAM control register 0x0000 0000 0x13010080
RTCSR Refresh time control/status register 0x0000 0x13010084
RTCNT Refresh timer counter 0x0000 0x13010088
RTCOR Refresh time constant register 0x0000 0x1301008C
DMAR SDRAM bank address configuration register 0x000020F8 0x13010090
SDMR Mode register of SDRAM bank -- 0x1301A000
  • DMCR: is a 32-bit R/W register that specifies the width of data and address buses, and controls the access mode of SDRAM, handling the size of addresses that might be written on banks: it also handles the timing.
  • SDMR: it controls the writing features of SDRAM, selecting which address will be the written.
  • RTCSR: is a 16-bit R/W register that specifies the refresh cycle and the status of RTCNT, defining the boundaries until counter reach for make a new refreshing cycle.
  • RTCNT: is a 16-bit R/W register that acts as a counter with input clocks and flag for refreshing.
    • RTCOR: is a 16-bit R/W register that is constantly compared with RTCNT, so when a match exits, it starts the memory refresh cycle.
  • DMAR: defines the physical address for SDRAM bank.

SDRAM interface supports a power-down mode, for minimizing power consumption, and also high-speed mode, for handling repeated accesses to the same row at the memory. It also offers the posibility to choose between auto-refresh and self-refresh modes depending the state of system.

[edit] SDRAM Timing

The SDRAM function is used for handling repeated accesses to the same row at the memory. As SDRAM is internally divided into two or four banks, it is possible to activate one row address in each bank. When a de-active bank is accessed, an access is performed by issuing an ACTV command following by READ or WRIT command. When an active bank is accessed and just hits the opened row, an access is performed by issuing READ or WRIT command immediately without issuing an ACTV command. Otherwise, if it hits a closed row, a PRE command is first issued to precharge the bank, then the access is performed by issuing an ACTV command followed by a READ or WRIT command.

[edit] Refreshing

The EMC provides a function for controlling the refresh of the SDRAM.

[edit] AUTO-refresh

Refreshing is performed at intervals determined by the input clock selected by bits CKS2-0 in RTCSR, and the value set in RTCOR. When the clock is selected by CKS2-0, RTCNT starts to act as counter from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the match exists, it starts the memory refresh cycle. At the same time, RTCNT is cleared to zero and it starts counting up again.

[edit] Bus Control Register

Is the register that is used to define boot configuration and also controls the bus accesses to avoid errors while an operation is being realized, due to that the bus is shared by the static interface and the NAND interface.

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