Software Hello World

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Below will perform the documentation for one aplication that display a message by the serial port platform. This is to explain the peripherals configuration of NanoNote: the SDRAM controller, Serial port and The internal clock generator.

For this we use the application xburst_stage1 which is part of tool usbboot.

This application is part of a tool that lets us downloads applications to the intermal memory of the Nano, The SDRAM or NAND. Its funtions are:

  • Configure and initialize the PLL.
  • Initialize SDRAM memory (32 MBytes) to allow storage and execution of applications greater than 16KBytes (Memory Size Internal).
  • Initialize the serial port as depuration means.
  • initializing GPIOs

Contents

[edit] Source Code

The files that are part of this application are:

xburst_stage1/
|-- Makefile        // File that defines the rules to make tool
|-- board_4740.c    // Peripheral initialization routines for the processor JZ4740
|-- board_4750.c    // Peripheral initialization routines for the processor JZ4750 
|-- common.c        // Functions for handling the serial port
|-- debug.c         // Routines to verify the operation of the SDRAM and GPIOs
|-- head.S          // Entry point application
|-- main.c          // Main routine
`-- target.ld       // Bound script.

[edit] C runtime Startup code 'head.S'

This file is the entry point for the application, is the first piece of code that will run and is charge to:

  1. 	.text
  2. 	.extern c_main
  3. 	.globl _start
  4. 	.set noreorder
  5. _start:
  6. 	b	real_start
  7. 	nop
  8. 	.word	0x0 /* address: 0x80002008 */
  9. 	.word	0x0
  10. 	.word	0x0
  11. 	.word	0x0
  12. 	.word	0x0
  13. 	.word	0x0
  14. 	.word	0x0
  15. 	.word	0x0
  16. 	/* reserve 8 words for args
  17. 	 * this is must big then sizeof(sturct fw_args)
  18. 	 */
  19. real_start:		
  20. 	/*
  21. 	 * setup stack, jump to C code
  22. 	 */
  23. 	la	$29, 0x80004000	/* sp */
  24. 	j	c_main
  25. 	nop
  26.  
  27. 	.set reorder
  • [Initialize the stack (Línea 23)]
  • [Call the C code. (Línea 24)]

[edit] board_4740.c

This file performs the configuration of the following peripherals:

[edit] General Purpose Input/Output (GPIOs)

The Funtiongpio_init_4740 initializes the CPU pins associated with NAND memory controllers (__gpio_as_nand), SDRAM memory (__gpio_as_sdram_32bit)and the serials ports (__gpio_as_uart0, __gpio_as_uart1).

  1. #include "jz4740.h"
  2. #include "configs.h"
  3.  
  4. void gpio_init_4740(void)
  5. {
  6.  
  7. 	/* Initialize NAND pins  */
  8. 	__gpio_as_nand();
  9.  
  10. 	/* Initialize SDRAM pins */
  11. 	__gpio_as_sdram_32bit();
  12.  
  13. 	/* Initialize UART0 pins */
  14. 	__gpio_as_uart0();
  15. 	__gpio_as_uart1();
  16. }

For example look at the function that configures the serial port pins defined in the file usbboot/xburst_include/jz4740.h

  1. #define __gpio_as_uart0()			\
  2. do {						\
  3. 	REG_GPIO_PXFUNS(3) = 0x06000000;	\
  4. 	REG_GPIO_PXSELS(3) = 0x06000000;	\
  5. 	REG_GPIO_PXPES(3) = 0x06000000;	\
  6. } while (0)


To allow the CPU pins are used by the peripherals associated with them is necessary configure for that, this is achieved by having the PXFUN register bit for each pin has the proper value, if PXFUN = 0 the pin can be used as GPIO or as interrupt input, if PXFUN = 1 the pin is configure for perform one alternate funtion if its asociated to a peripheral. In this case its writing a 1 (Line 3)in bits 25 and 26 of port 3 (GPD25 and GPD26) PXFUN registry port D, then we associate with TXD and RXD signals to ports GPD25 and GPD26 respectively.

When PXFUN = 0, if PXSELX = 0 is used as GPIO, if PXSELX = 1 is used as interruption source. When PXFUN = 1, if PXSELX = 0 is assigned the alternate function 0, if PXSELX = 1 is asigned the alternate function 1. For this example assigns the value 1 to bits 25 and 26 of the port 3 register PXSEL thus assigned alternate function 1 to these pins( UART ) (This pin also has 2 outputs associated PWMs ).


Finally, it writes a 1 in 25 and 26 bits of PXPE register, which disables the internal pull up/down pins GPD25 internal and GPD26.

Similar actions are performed to the associated pin to NAND, SDRAM and UART1.

[edit] PLL

  1. void pll_init_4740(void)
  2. {
  3. 	register unsigned int cfcr, plcr1;
  4. 	int n2FR[33] = {
  5. 		0, 0, 1, 2, 3, 0, 4, 0, 5, 0, 0, 0, 6, 0, 0, 0,
  6. 		7, 0, 0, 0, 0, 0, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0,
  7. 		9
  8. 	};
  9. 	/* int div[5] = {1, 4, 4, 4, 4}; */ /* divisors of I:S:P:L:M */
  10. 	int nf, pllout2;
  11.  
  12. 	cfcr = CPM_CPCCR_CLKOEN |
  13. 		(n2FR[1] << CPM_CPCCR_CDIV_BIT) | 
  14. 		(n2FR[PHM_DIV] << CPM_CPCCR_HDIV_BIT) | 
  15. 		(n2FR[PHM_DIV] << CPM_CPCCR_PDIV_BIT) |
  16. 		(n2FR[PHM_DIV] << CPM_CPCCR_MDIV_BIT) |
  17. 		(n2FR[PHM_DIV] << CPM_CPCCR_LDIV_BIT);
  18.  
  19. 	pllout2 = (cfcr & CPM_CPCCR_PCS) ? CFG_CPU_SPEED : (CFG_CPU_SPEED / 2);
  20.  
  21. 	/* Init UHC clock */
  22. 	REG_CPM_UHCCDR = pllout2 / 48000000 - 1;
  23.  
  24. 	nf = CFG_CPU_SPEED * 2 / CFG_EXTAL;
  25. 	plcr1 = ((nf - 2) << CPM_CPPCR_PLLM_BIT) | /* FD */
  26. 		(0 << CPM_CPPCR_PLLN_BIT) |	/* RD=0, NR=2 */
  27. 		(0 << CPM_CPPCR_PLLOD_BIT) |    /* OD=0, NO=1 */
  28. 		(0x20 << CPM_CPPCR_PLLST_BIT) | /* PLL stable time */
  29. 		CPM_CPPCR_PLLEN;                /* enable PLL */          
  30.  
  31. 	/* init PLL */
  32. 	REG_CPM_CPCCR = cfcr;
  33. 	REG_CPM_CPPCR = plcr1;
  34. }

[edit] SDRAM

[edit] Serial port

[edit]

[edit]

[edit] common.c

[edit] debug.c

[edit] target.ls

[edit] Nano Compilation and transfer

The Figure below shows the steps to be followed in order to run this application on the Nano platform..

SW design flow.png

[edit] Compilation

To generate the binary file to be downloaded to the platform must be installed on the Toolchain GNU, and optionally define the variable crossmake to:

$ alias crossmake='make ARCH=mips CROSS_COMPILE=mipsel-openwrt-linux-'

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