SIE V2 prototype reflash and test
NOTE, SAKC has been renamed SIE. So, some places SAKC is referred to as SAKC.
This page is to record that how we test SIE V2 65pcs during SIE run 2 schedule prototype run. This is irreverent pages into official image. Since we haven't built sufficient production software, the simple test plan for this run will be also discovered here.
 SIE V2 Quiescent and working Current
If the SIE has never been reflashed, its normal quiescent current must be around 90mA(in usb boot mode). With this info, we can measure this current first to make sure the manufactured/mounted SIE without failures caused by manufacturing process. If a current goes larger or less than 90mA +/- 20%, which probably mounted not well. So need to check as well.
|Conditions||Power Supplied by USB Cable||Reflashed||LCD connected||uSD Inserted||Measured current(A)|
 SIE V2 reflash Steps
Current steps of reflash SIE has been contributed by Carlos, Mirko Vogt and Xiangfu. Here's only for this trial run purpose not an official sources. Please always read or take care of subscribing list to know up-to-date news.
 Load u-boot
 Reflash Kernel
 Program Root File System
 Report of SIE V2
Report below is mostly referred to Hardware Hello World. There's several exercises introduced for FPGA or jz4725. So using those tools and utilities to test some chips on SIE board. The report here doesn't include tests:
jz4725's I2C(J6 & J7), all J16's pins. FPGA's DIG0~DIG24 DC JACK (J17, not mounted), PB3 Switch BT1 schematic, the value of R34 is 1K ohm presently suggested by Carlos.
All others functionality of all chips and connectors must be completely tested in results as table below:
Voltage column is referred to [Voltage]. D7 is always ON.
Current column is referred to SIE V2 Quiescent and working Current.
Reflash LED D1 column is referred to reflash and test. D1 is blinking.
LCD column is to check if the screen displayed well while reflashing.
ADC column is referred to ADC test with scope views. This is for two channels test. There's another 8 channels tools can be used TestADC. So can transfer this file into SIE and do the same steps as ADC test with scope views.
Serial column is referred to serial connection between jz4725 and FPGA.
Micro-SD column is referred to Micro-SD test result and used http://projects.qi-hardware.com/index.php/p/nn-usb-fpga/source/tree/master/binaries/sie_rootfs_files/root/binaries/test-memory-card.sh to test.
CPU RESET column is to press PB1 Tact switch to test U12 chip MIC811TUY function and let CPU reset.
FPGA RESET column is to press PB2 Tact switch to test U9 FPGA reset.
LED D6 column is to use Some usefull program to test SIE's jz4725 to test LED D6.
LED D7 column is mean that when 3V3 is present, this D7 must be ON.
report source updated on 20110324
|SIE PCBA#||Voltage||Current||Reflash LED D1||LCD||ADC||Serial||Micro-SD||CPU RESET||FPGA RESET||LED D5||LED D6||LED D7||Reasons||Root Cause||Deliver to whom
|8||V||V||V||V||X(8 channels scope no show)||V||V||V||V||V||V||V||use 'ps -fea' but there's no ./TestADC process shown up, so program rootfs again then works well.||don't know||CARLOS|
|9||V||X(0.06A)||X(cannot boot)||V||V||V||V||V||V||V||V||V||1, the total current is only 0.06A, so cannot enter boot status. 2, A small solder splash short between C6 and R4 to cause this.||This caused by taking off BT1 battery' rework results, and factory didn't clean well||CARLOS|
|10||V||V||V||X(over 0.35A)||not yet||V||V||V||V||V||V||V|
|18||V||V||V||V||X(8 channels shows 2 waveforms from each input)||V||V||V||V||V||V||V||after programming rootfs, it works||don't know||cristian paul|
|22||V||V||V||V||X(8 channels shows more waveforms from each input)||V||V||V||V||V||V||V||replaced FPGA & ADC chip, still no good|
|23||V||X(0.06A)||X(cannot boot)||V||V||V||V||V||V||V||V||V||RTC 32.638KHz doesn't work, after either replacing a new Y1 or replaced 10pF for C3&C4. It's ok. And got 0.09A before reflashing.||This needs to be figured out what input/output capacitance of jz4725 from Ingenic to fine tune C3 &C4.||CARLOS|
|24||V||V||X(can't retrieve XBurst CPU information: -110
|replaced a new CPU but still no work|
|26||V||V||V||X(over 0.35A)||not yet||V||V||V||V||V||V||V||Diego|
|36||V||V||X(can't retrieve XBurst CPU information: -110
|no 12MHz, static current is shift||Diego|
|39||V||V(static 0.12A)||V(D1 no ON)||A small solder splash short between cpu pin 6 & pin7.|
|47||V||X(over 0.35A)||V||V||V||V||V||V||V||V||V||V||A small solder splash short between C65 and C74 to cause this.||samw as #9||DAVID|
|52||V||V||X(D1 no ON)||V||V||V||V||V||V||V||V||V||R30 is defective.||-||CARLOS|
|57||V||X(0.06A)||V||V||V||V||V||V||V||V||V||V||same as #23||same as #23||CARLOS|
|59||V||X(0.07A)||V||V||V||V||V||V||V||V||V||V||same as #23||same as #23||DAVID|
|60||V||V||V||V||X(8 channels scope no reply on each channel)||V||V||V||V||V||V||V||FPGA pin64 cool soldering||let SMT vendor know||DAVID|
|61||V||V||V||V||X(8 channels scope no reply on each channel)||X(D5 always HI after config ./plasma.bit)||V||V||X(no reply)||X(no blinking)||V||V||Diego|
|64||V||V||V||no screen||not yet||V||V||V||V||V||V||V||Diego|
 Some Videos & Pictures during manufacturing
Some processes have been recorded here not all, if you would like to see a whole process of mounting and through hole, please refer to Milkymist One SMT/DIP Process Flow for more in details.
SMT reflow machine profile and factory's internal doc.
 V2 errata
 Major errors
1, Cannot power SIE from DC jack and mini-USB connector at the same time, see here.
2, BT1's footprint is reversed polarity. On V2 for all boards the BT1 is unmounted. A standard CR series battery holder could be instead of rechargeable battery, see here.
3, RTC Y1's 32.768KHz schematic C3/C4 needs to be fine tuned. Due to Y1's Cl = 12.5pF, so needs to refer to Equivalent Circuit and Paramenters of Crystal and do a fine-tuned experiments first. The z4720's input & output capacitance must be provided from Ingenic.
4, U11's footprint does not meet its specification.
 Minor errors and improvements
1, C74 needs a footprint 1206 package for general 10V, 10uF, 10%, SMD part.
2, C65 could be changed into a 0805 package for general 16V, 4.7uF, 10%, SMD part.
3, Given "+" mark around at positive solder pad for all diode and led, and smt machine can easily and effectively set up.
4, If C12, C14, C17, C18, C29, C56 and C74 are using TANTALUM type of capacitors, also given "+" mark around at positive solder pad for them is preferable.
5, Request smt factory that even if some reworks are done, the processes of AOI or manual inspection must be executed.
6, Enlarge more solder area under the Tab(Vout) pad of U7 and U8 to increase area of propagating heat.
7, Enlarge more solder area on 4 case pads of J1 uSD socket to get more stronger solderability.
8, Can align and merge J18 with J6/J7 into a whole 2*5pins part, they are all 2.54 mm pin headers.
9, Try out an more easy architecture to assemble LCM and SIE main board, refer to here.
10, Using a cheaper ADC instead of U11 TLV1548IDBRG4.
11, Using through holes footprints for Y1 & Y2 instead of SMD soldering pads, but keeping lying low bearing. This can simplify and reduce processes during manufacturing.
12, Enlarge the three soldering pads of DC Jack(J17).
 Unknown Issues
1, Don't know why sometimes need to press twice "xc3sprog ./blink.bit" commands which porting bit stream file into fpga to make it work? Not sure s/w or h/w caused it. Same some commands using other "xc3sprog ./****.bit".
2, Descovered two tests of pcba #8 and #18 that indicated ADC samples function works well after twice programming rootfs file.