SAKC V2 run test plan

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A Test Plan is aimed to cover all parts successfully tested and make sure functionality are qualified. Especially design for manufacturing large quantities on production purpose. The initial test plan should be at least cover criteria below. Here is for the example proposed Test Plan of SAKC V2.

[edit] Connection of Test Board with SAKC V2

Connection of Test Board with SAKC V2, file

[edit] Test Criteria about production software / test plan

Test Criteria is to make sure assembled V2 from manufacturer having good quality. A production software must meet this criteria to pass them all. Here criteria below are designed and based on V2's features/schematic, thus is to completely verify all mounted parts having good soldering quality.

a) All connections of 40pins on J19 FPGA extendable header can transmit signals well. This can be tested by adding a small test board with female/receptacle connector to connect it, includes 3.3V and GND. This header includes:

 -- DIG0~DIG23 from spartan-3, test the traces from fpga if connected well.
 -- Power Supply +3.3V, Digital GND, test the power connections of traces are good
 -- ADC_VREF, test if the trace voltage is good from external to determine maximum input voltage range between the voltages applied to REF+ and REF–. This can be connected to 3.3V directly.
 -- ANALOG0~7, to verify the traces from TLV1548IDBRG4 if connected well.
 -- AN_GND 

b) All connections of J20 LCM module connector work well. This needs a LCM plugged into J20 to check if video signals on screen are good and acceptable. c) J16 header for extending jz4725 audio CODEC function and verify the traces for audio IN/OUT, MIC, AD if connected well. This can be tested by a small test board with female receptacle to connect J16 header.

 -- ADIN0~1, to test ADC general purpose input 0~1
 -- L-HPO / R-HPO, test Left/Right headphone out
 -- R-LINEIN / L-LININ, test audio Left/Right input
 -- MICIN, test Microphone input

d) If indicators work well

 -- D1 (LED), to indicate jz4725's UART0 on status of TX signal activates.
 -- D5 (LED), to indicate when push tact switchs or signal activates it from fpga.
 -- D7 (LED), to verify if +3.3V supply well when following power conditions set up:
       1) external USB power +5V coming with shorting J18, or
       2) DC Jack J17 +5V coming,

e) If all signals go through J6 and J7 headers are good

to verify if serial & I2C interface work well, this can be tested by adding a small test board with female/receptacle to connect J6 & J7, includes 3.3V and GND.

 -- J6 - TX1/RX1, to test jz4725's UART0. Plan to use simply short loop to let it as loop back.
 -- J7 - TX2/RX2, to test Spartan-3E fpga's serial function. Plan to use simply short loop to let it as loop back.
 -- J6 & J7 - SDA/SCK, to test jz4725's I2C interface, This can use a 2-WIRE SERIAL CMOS EEPROM to match it.

f) If USB device function and +5V power comes from J8 mini-USB connector. A successful re-flash steps can make sure this.

g) Supply +5V power to V2 by DC Jack( J17 ) come with a short jumper on J18. And it works well.

h) Supply 3V Battery to V2 by BT1 (HB414-IV01E) HB Lithium Rechargeable Battery

i) If USB boot function by using jumper on J15 works well. This can be tested same as f).

j) Tact switch Function

 -- PB1 - RESET, reset V2
 -- PB2/PB3 , test and show its reaction.
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