Power On Reset

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In order to be sure about Nano operation, all external voltages used in JZ4720 need to be supplied with a specific sequence, As you can see in the next image. Each one of them are explained in the next table.

Is very important that the supply order inside the processor keeps as next: 1 VDDRTC

2 VDDA: VDDCDAC, VDDCADC, VDDLHP, and VDDRHP
3 Each one of 3.3V VDDs (VDD33): VDDIO, VDDADC, and  VDDUSB
4 Each one of 1.8V (VDD18): VDDCORE, and VDDPLL

Times.jpg Table

Each tension is supplied according to the kind of component requiring it. Next we can see tensions supplies required by Nano components. Powerthree.jpg

JZ4720 SoC has an operating frequency of 366Mhz as maximum. It offers an input/output tension of 3.3 ± 0.3V, Core: 1.8 ± 0.2. Power consumption depends on the actual operating frequency. i.e 240MHz needs 150mW.

Inside arch/mips/include/asm/mach-jz4740/regs.h file, there are defined te files in charge of POWER MANAGEMENT.


/*************************************************************************

* CPM (Clock reset and Power control Management) 
*************************************************************************/ 

/* Low Power Control Register */

  1. define CPM_LCR_DOZE_DUTY_BIT 3
  2. define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT)
  3. define CPM_LCR_DOZE_ON (1 << 2)
  4. define CPM_LCR_LPM_BIT 0
  5. define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT)
 #define CPM_LCR_LPM_IDLE	(0x0 << CPM_LCR_LPM_BIT) 
 #define CPM_LCR_LPM_SLEEP	(0x1 << CPM_LCR_LPM_BIT) 

/* Sleep Control Register */

  1. define CPM_SCR_O1ST_BIT 8
  2. define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT)
  3. define CPM_SCR_USBPHY_ENABLE (1 << 6)
  4. define CPM_SCR_OSC_ENABLE (1 << 4)

/* Hibernate Control Register */

  1. define CPM_HCR_PD (1 << 0)

/* Wakeup Filter Counter Register in Hibernate Mode */

  1. define CPM_HWFCR_TIME_BIT 0
  2. define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT)

/* Reset Counter Register in Hibernate Mode */

  1. define CPM_HRCR_TIME_BIT 0
  2. define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT)

/* Wakeup Control Register in Hibernate Mode */

  1. define CPM_HWCR_WLE_LOW (0 << 2)
  2. define CPM_HWCR_WLE_HIGH (1 << 2)
  3. define CPM_HWCR_PIN_WAKEUP (1 << 1)
  4. define CPM_HWCR_RTC_WAKEUP (1 << 0)

/* Wakeup Status Register in Hibernate Mode */

  1. define CPM_HWSR_WSR_PIN (1 << 1)
  2. define CPM_HWSR_WSR_RTC (1 << 0)

/* Reset Status Register */

  1. define CPM_RSR_HR (1 << 2)
  2. define CPM_RSR_WR (1 << 1)
  3. define CPM_RSR_PR (1 << 0)


Reset

Three reset sources can be presented, PPRST_pin reset, WDT timeout and hibernating reset. After reset is produced, boot Is initialized. The first reset is shown when PPRST_N has a logic value of 0, and it happens when RESETK key of Nano is pressed or when RTC power is set on. Here, all the internal modules go back to its predefined start state.

WDT (watchdog timer) reset is activated due to the system bad functioning, such as noise or any kind of error. Finally we have the Hibernate reset mode. It is enabled when it recognize WAKEUP_N signal, caused by Nano ONOFFK key. After CPU reset, and all the peripherals are synchronized by the 12MHz directly, the PLL goes back to its off state too, and the internal modules are initialized to its reset state.

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