Milkymist One RC2 Layout History

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The histories here are the whole relationships between placements, layout criteria and relevant routings. All the info here you can take a look or reference. We're trying to record all the concerns of how routing, how this moving on and what did we do. No matter what we might encounter a wrong direction potentially or even correct direction. So we encourage people who possesses solid experiences in this layout industry to have fun and give us feedbacks which could nourish this copyleft hardware as an amusement park here.

Contents

[edit] 20101108_final

Changed Silkscreen text to be "20101108".

[edit] 20101105

This version is to fix DRC error and SchLib file which is not to date. Check here and its following emails.

[edit] 20101102

This version is based on http://lists.milkymist.org/pipermail/devel-milkymist.org/2010-October/000994.html And the following items have been changed:

 1, U10 pad1/3 dimension is 66.929 x 51.181 mil.
 2, Fixed & Updated MilkymistOne.SchLib(no Footprint preview available), MilkymistOne.PcbLib, MilkymistOne.LibPkg(no re-compiled)

This version has three classes of Rule Violations which totally over more than 500 items when you execute DRC: This version we didn't disable some DRC rules, we'll disable them surely before going for gerber out.

  • 1), 388 items of [Matched Net Lengths(Tolerance=200mil) (Amplitude =200mil) (Gap=20mil) (Style=90-Degree) (InNetClass('All Nets'))], ruled by 'Default' PADS rule_7 of Matched Net Lengths of High Speed. This is used on designing High Speed pcb with specified Tolerance, Amplitude, Gap and Style elements. Xilinx uses FPGA's IODELAY elements to compensate for signal propagation delay discrepancies,so such contrary to length-equalizing (and length-increasing) zigzags. RC2 no needs this.
  • 2), 83 items of [Parallel Segment Constraint (Gap=200mil ) (Limit=1000mil) (All),(All)], ruled by 'Default' PADS rule_2 and 'Default' PADS rule_3 of Parallel Segment of High Speed. PADS rule_2 is for same layer checking for a parallel gap of 200mil, the parallel limit length is 1000mil. PADS rule_3 is for adjacent layer checking which is same as rule_2. Both RC2 don't need them.
  • 3), 29 items of [Hole Size Constraint (Min=1mil) (Max=100mil) (All)], ruled by HoleSize of Hole Size of Manufacturing. This Hole Size is ruled from minimum 1 mil to 100mil. In a general, actually one pcb uses several 'Hole Size' of vias and pads.

The above three Rules Violations can be disable on RC2. RC1 was disable.

[edit] 20101028

[edit] 20101018

  • Enhance DDRRAM power noise immunity:
  • Strengthen independantly power or ground driven pin of FPGA:
  • Added routing for parts of 4.3V Power Supply
  • Given several vias to connect decoupling capacitors whenever possible, especially the big ones. See below.

[edit] 20100929

  • Strengthen independantly power or ground driven pin of FPGA:
 Corrective Action: In Fg. 3 that shows most of 1V2 or ground pins of FPGA share with one via source. 
 This must be corrected with using at least 1 via for each power or ground pin of FPGA.

In Fg. 1 shows that each pin of FPGA connects to each only one via. This approach is resorted to a more layers like this is a 16-layers pcb. The L16_BOTTOM layer is in dark gray color, L1_TOP layer is in light gray color, L15_PWR is power layer, L2_GND(not shown) and SILK_BOT is in red color. To let a 6-layers stacking with all power and ground pins connected to each independant via sometimes is not possible but wherever possible.

  • Enhance DDRRAM power noise immunity:
 Corrective Actions: In Fg. 1 that needs to add 100uF at nearby pins 1/18/33 each for VDD, and add 100nF
 at nearby pins 3/9/15/55/61 each for VDDQ. Same methods at U15 in Fg. 3. Also add several vias to 
 connect decoupling capacitors whenever possible, especially the big ones (100uF). With adding more
 capacitors corrected in Fg. 2 and 4. Big squares are 100uF, the small squares are 100nF.

From Micron TN-46-14 p.14 subtitle of Decoupling, it said that VDD is digital power for the device core and VDDQ is power for the DQ and I/O signals. So recommends at least four low (2nH) effective series inductance (ESL) capacitors per DDR component to decouple VDD/VDDQ from VSS/VSSQ. Values from 0.01–0.22μF balance well in bypassing higher-frequency (0.01μF) and lower-frequency (0.22μF) noise. If a frequency spectrum characterizing power-supply noise can be generated, choosing capacitors to optimize decoupling at certain frequencies (where noise peaks)is preferred. Associated technical note called "DECOUPLING CAPACITOR CALCULATION FOR A DDR MEMORY CHANNEL" goes deep into technical parameters determined with via. Although it recommends to use a low ESL capacitor which always have higher price than general purpose MLCC (Fg. RC1 C162/100nF/X5R). So just adding and keeping using more capacitors used in RC1 seems a good solution.

  • Given several vias to connect decoupling capacitors whenever possible, especially the big ones.

The following pictures are all being needed to add more vias at the pads of decoupling capacitors, especially the 100uF(1210 package). Although these bad routing do not alter the functionality of the RC1 board, we still can give improvement on them.

  • Planed a placement area for parts of 4.3V Power Supply
  • Improvement solderibility during SMD reflowing

[edit] See also RC1 Layout History

[edit] Milkymist One RC1 Layout History

[edit] Link

[edit] Reference

  1. TOMBSTONING OF 0402 AND 0201 COMPONENTS: "A STUDY EXAMINING THE EFFECTS OF VARIOUS PROCESS AND DESIGN PARAMETERS ON ULTRA-SMALL PASSIVE DEVICES"
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