Milkymist One RC1 Layout History
The histories here are the whole relationships between placements, layout criteria and relevant routings. All the info here you can take a look or reference. We're trying to record all the concerns of how routing, how this moving on and what did we do. No matter what we might encounter a wrong direction potentially or even correct direction. So we encourage people who possesses solid experiences in this layout industry to have fun and give us feedbacks which could nourish this copyleft hardware as an amusement park here.
The final design files are under there. For the gerber files are under here.
Expanded limited( no parts ) area on J9 and J10 to reserve more space if using substitution (Eg. SCN600S50S00000G) which have 19 mm long body.
Determined all final footprints of IO connectors.
Milkymist_logo.png is placed at top/bottom side silk layer. Text: GND, RX, TX, 3V3 , JTAG, DC 5V IN , DMX RX, DMX TX, MIDI RX, MIDI TX, LINE IN, LINE OUT on related connectors
R62 wiring to be 8 mil and placed at bottom side.
Make a clear pin1 mark on U3.
CLEARANCE for J4: Make a clearance between connectors(J12~J15 / J16 / J17 / J20 / SW1~3) shielding and GND plane. (Same as J4 method) See also here for
Put 4 more vias on the GND terminal of L11.
Milkymist One interactive VJ station RC1 201005??, the final date will be given once gerber out. Copyleft Hardware cc-by-sa-black-white.jpg Design: www.milkymist.org Manufacturing: www.sharism.cc Routed a track of 10 mil connected to the right side GND vil of U2_pin39_GND.
CD-GND netlist is changed to 15 mils from J3.pin9 to U1.pin19 Put 2 more vias on 5V pad between C33 and L2. Same as C33's terminal GND. Let C33 and C35 to be placed in parallel. The +5V routing must be went through sequentially PI-type filter network composed of C33/L2/C34. Those kinds of filter network should be at the same side.
Put 1 more via on the polarized side of C179 to bottom layer. Routed individual track for U18.pin14~15 to GND plane. Same as U18.pin39~40。 Given 1 more via on C230's 1V8 trace. Given 1 more via on C222's 3V3 trace.
Changed their track thichness to 8 mil on relevant Q1/Q2/U19/U20. Using GND shieding method to shield net <VGA_CLK> of U18.pin24 on in1 layer. Routed U21.pin34's GND by via method not using the GND which is used for digital VIDEOIN in1 layer Routed & Made net <NETU21_20> to be shielded in in1 layer with GND shieding covered. It's a 27MHz clock. Thus alighment is like GND//NETU21_20//GND. Eg. GND//NETU21_53//GND, GND//NETU21_54//GND. Let R158/R159/R160/R161 those four resistors close together to be settable when Hi/Low settings. Also marked FPGA_M0 and FPGA_M1 text on Silkscreen layer.10, ETHERNET Routed net NETU2_46 <ETH_CLK> with shielding in in1 layer.
According to a recommended DDR routing topology, especally the R91's route we changed for being a better route suggested by "Single CK–CK# Differential Resistor Placement at Split Point" from p13 of Micron tn4614.pdf said. Compared to previous routing which was violated this conceipts.
Connected U9.pin31 BYTE# to VCCO_1 (3V3) Terminate the end of the CCLK transmission line with a parallel termination of 100Ω/R164/1%/0402 to VCCO and 100Ω/R165/1%/0402 to GND (the Thevenin equivalent of VCCO/2, and assuming a trace characteristic impedance of 50Ω). Route the CCLK net as a 50Ω controlled impedance transmission line. Stubs, if necessary, must be shorter than 8 mm (0.3 inches).
Check microSD card pinout: ref. to 1, 2. If routing allows: ** in order to increase Flash bandwidth, connect D8-D15 to the FPGA (there must be connected to special pins, indicated on the schematics symbol, because the Flash is used for configuration). For 16-bit, the Flash's BYTE# pin must be connected to 3.3V VCC (not FPGA's LDC or ground). See Xilinx UG380 p.48 1. If you switch the flash to 16-bit, addresses must be reorganized. The Flash's A0 should be grounded (the flash datasheet says (p.6) this pin becomes unused, but it's safer to ground it than to leave it floating), FPGA's A0 should be connected to Flash's A1, FPGA A1 -> Flash A2, etc. (see configuration waveform on UG380 p.50). ** add an expansion header and route spare I/Os to it. See 2.