Milkymist One Power On Off Sequence

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[edit] Normal RC2 Power On Off Sequence

[edit] Known un-booted conditions

Fig. 2, With Sch. 1. How "fast" power cycling it is!


When unbooted condition is happened, the LED D2,D3 lights slightly. You probably can boot next power plug-in or never boot at all forever.

  • Rarely happens - have the intermittent no configuration problem whose symptom is LEDs(D2, D3) weakly lit after power up and no boot at all (no serial output). even power adapter plugs-in (start-up).
  • Often appears: power on then off, and power on again with tiny duration said like below 200ms. (fast power cycling)

Questions:

1. Does Program_B pin of the waveform rising time being consistent with Xilinx specifications? See Problem 1 of Fig. 2. Answer: No! Check here.

2. Does Program_B pin get low at least 500ns before pulling high to asserting a start of configuration? See Problem 2 of Fig. 2. Answer: No! The level is probably recognized as an unknown one for a VIL even there's no actual low level asserted to restart a FPGA configuration! This is a similar phenomenon also occurs in U9 RP# pin when fast power cycling, see Fig. 9 and 10.

3. Is it necessary that PROGRAM_B synchronizes reset activation with NOR FLASH? Answer: Yes, check NOR FLASH Reset Specifications.

From above questions, RC2 design already exactly have ran into this issue especially when fast power cycling.

[edit] The schematics of three experiments

[edit] Configuration Sequence

Fig. 3, FPGA Cofiguration Sequence


[edit] Usefull pin of FPGA Configuration

  • PROGRAM_B : It's a dedicated input pin for Active-Low asynchronous full-chip reset. When asserted Low for 500 ns or longer, forces the FPGA to restart its configuration process by clearing configuration memory and resetting the DONE and INIT_B pins after PROGRAM_B returns High.
  • During Configuration: Must be High to allow configuration to start.
  • After Configuration: Drive PROGRAM_B Low and release to reprogram FPGA. Hold ROGRAM_B to force the FPGA I/O pins into High-Z, allowing direct programming access to SPI flash PROM pins.

[edit] Power-On Sequence Precautions for FPGA[5].

One of the following system design approaches can ensure that the SPI flash is ready to receive commands before the FPGA starts its configuration procedure:

1. Control the sequence of the power supplies such that the SPI flash is certain to be powered and ready
 for asynchronous reads before the FPGA begins its configuration procedure.
2. Hold the FPGA PROGRAM_B pin Low from power-up to delay the start of the FPGA configuration procedure
 and release the PROGRAM_B pin to High after the SPI flash is fully powered and is able to receive 
 commands.
3. Hold the FPGA INIT_B pin Low from power-up to delay the start of the FPGA configuration procedure and 
 release the INIT_B pin to High after the SPI flash becomes ready to receive commands.

Since this statement describes about SPI flash, but its explaination is still usefull to other derivatives. It especially expresses why our boot bug could be also happened on BPI NOR flash.

[edit] JS28F256J3F105[6] NOR FLASH Reset Specifications

It's power supply sequencing is not required if VPEN is connected to VCC or VCCQ. In this Milkymist One's design, the VPEN is thus connected to VCC and VCCQ. It's thus 3V3 net. But Power supply transitions should only occur when RP# is low. This protects the device from accidental programming or erasure during power transitions. Unfortunately the RC2's design doesn't take this consideration. From Normal RC2 Power On Off Sequence, we can see RP# almost goes high which shows it synchronized to VCCQ! But data sheet says at least 300us for VCC power valid to RP# high level. Check following waveform scoped which indeed violates recommendation.

Asserting RP# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RP# to the same active low reset signal used for CPU initialization. Also, because the device is disabled when RP# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. See Reset Operation Waveforms in JS28F256J3F105.

1, tVCCPH: Min. 300us, VCC Power valid to RP# de-assertion (high)
2, tPLPH: Min. 100ns, RP# pulse width low

[edit] Results

  • 0x2c board with Sch. 3:

A) 1. After 1000 times normal power on test, the start up bug on D2 D3 weakly lighting without configuration from failure loading standby stream is fixed. This shows that fpga always correctly loads its STANDBY bitstream (ie that waits for the middle pushbutton press) after power is applied. We verified that checking for a configured FPGA can be done by checking that the LEDs are off (not weakly lit) and/or that the DONE pin is high. Do not press any pushbutton, just apply power and check the FPGA configures itself.

B)1. After fast power cycling about 9 or 10 times, got msg log below, with D2 lights well, D3 is OFF.

2. forgot to capture waveform on this, power off then on; reflashing image again 3. After reflash, power-on then press mid-switch, D2 lights but screen shows nothing (in black) anyway 4. power off and wait for about 1 hr(just for lunch) 5. then power-on again, from now on; m1 easily enters unbooted more even just when power on. So tried to get and screen shows, D2 light well, D3 is OFF:

libHPDMC SDRAM initialization runtime
(c) Copyright 2010 Sebastien Bourdeauducq, released under GNU LGPL version 3.
Version 1.0RC1

Initialization sequence completed.
Autocalibration OK, testing memory...
Memory test failed, entering manual mode.

u: inc. DQ delay  // d: dec. DQ delay
t: test (small)   // T: test (large)
c: calibrate IODELAY2s
r: reset IODELAY2s
p: display pattern
b: boot
019

6. then board is always unbooted, so waveforms measured as below:

7. after 1.5 days later, can't understand why it revivified after long time? Power cycle then booted and entered Flicknoise with wrong background color, move mouser to the left upper corner then it just stops and can not be movable more. See below.

8. power cycle again, show logo, then shows "No boot medium found" again, same as Fig. 14.

9. Comparisons of h/w patched with good booted(board 0x14, Sch. 1) and bad unbooted(board 0x2c, Sch. 3): yes, there's images lost after address 0x02920000h about flicknoise. But how's existed important info related with steps 8?

C) 1. I reflashed 0x2c with normal xilinx tool back to a whole new image.

2. Using 'jtag' tool to reflash with msd-dec2010.tar.bz2.

3. Tried to click "Reboot" button successfully on Flickernoise 0.2 about 6 ~ 7 times then later serial/vga screen msg jumped into >BIOS shown as "No boot medium found"?

4, then type cmd 'reboot' in serial console then M1 shows up normal control panel again? What possible reasons will cause it?

[edit] Dump Procedures

Using UrJtag, type instructions below under jtag>

cable milkymist 
detect 
instruction CFG_OUT  000100 BYPASS 
instruction CFG_IN   000101 BYPASS 
pld load fjmem.bit 
initbus fjmem opcode=000010 
frequency 6000000 
detectflash 0 
endian big 
readmem 0 0x02920000 memory1_dump

Notice: Before doing comparisons, make sure hexdump and gvimdiff are installed:

# apt-get install bsdmainutils vim-gtk vim-runtime vim-gtk 
//frist convert dumps to text 
hexdump -C 0x2c_memory1_dump  > 0x2c_memory1_dump_text 
hexdump -C 0x14_memory1_dump  > 0x14_memory1_dump_text 
// once in text compare 
gvimdiff 0x2c_memory1_dump_text 0x1c_memory1_dump_text

[edit] Reference

  1. Original Milkymist One RC2 schematic
  2. A4806E3R-30N low voltage detector with 20us delay
  3. A4809E3R-263DN low voltage detector with 200ms delay
  4. Reset IC with 20us delay
  5. Xilinx UG380 Spartan-6 FPGA Configuration User Guide
  6. Numonyx JS28F256J3F105

[edit] Links

Operating Voltages of Milkymist One's Key Parts

Milkymist One RC2 Collective Waveforms Captured While Power On Off

Spartan-6 - Why is INIT_B low after power-on?

Xilinx UG394 Spartan-6 FPGA Power Management User Guide

Configuring Xilinx FPGAs with SPI Serial Flash

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Diodes Inc. DFLS120L-7 1.0A SURFACE MOUNT SCHOTTKY BARRIER RECTIFIER Forward Voltage 0.32 Typ. IF = 1.0A

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