Milkymist One Layout Criteria

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Paying more attention on any layout suggestions from datasheet of critical parts is to make good route solutions and get reliability expectedly while layout process. Here is to summarize those information including general rules and strongly recommended reminders. You could face this stage to build your expectative performance like check list which might reach results as same as chip provider suggested.

[edit] Schematics Symbols Review

  • Check for stupid errors like swapped or missing pins.

[edit] Footprint Review

  • Compare all data (pin numbers, geometries, plated/non-plated holes, ...) in the footprint libraries with the drawings in the datasheets.

[edit] Power Traces

  • Any power traces please reference its load conditions, so need to ref. to schematic & Milkymist One Power Tree.
  • Any power trace goes from ICs' in/output pad to next part's pad must at least keep same width as parts recommended width. Do not narrow trace width.
  • Allocations and layouts about power and ground Via, please also follow reference designs of Xilinx SP601.

[edit] FPGA layout

[edit] FPGA pins assignment

  • You can swap pins to make routing easier, but be careful of the special function pins (global clock capable pins, and pins that have a special behaviour during configuration). Most pins going to the Flash are not swappable because the Flash is used to configure the FPGA.

[edit] DDR SDRAM layout

  • A good document is available from Micron: http://download.micron.com/pdf/technotes/DDR/tn4614.pdf This document also recommends PCB layer stackups that we should use. I would choose the 4 signal layers option with 2 power planes. We'll use series terminations only with very short traces going to the FPGA. Do not spend too much effort on equalizing trace lengths. We have the FPGA's IODELAY elements to compensate for signal propagation delay discrepancies, and, contrary to length-equalizing (and length-increasing) zigzags, they do not cause additional signal integrity issues (ringing, noise, etc.). If you have time and an IBIS simulator, it would be a good idea to run a signal integrity simulation on the final routing. IBIS models for the FPGA's I/O cells can be downloaded from http://www.xilinx.com/support/download/sp6ibis.htm and those for the DRAM: http://download.micron.com/downloads/models/ibis/sdram/ddr/512meg/t37z_ibis.zip

[edit] Ethernet Routing

[edit] ESD Protection

  • As you may have noticed, there are several ESD protection cells made of a 1M resistor and a 4.7nF capacitor in parallel. You may want to cut the ground plane and add a little metal polygon under and around the concerned connectors, connected to their shells. Then place that ESD protection cells between the polygon and the ground plane. The Zener diodes near the DMX connectors are not meant to protect against ESD, but against clumsy users connecting microphone cables with 48V phantom power to the DMX plugs.

[edit] Video Decoder

  • POWER SUPPLY DECOUPLING, Using a single ground plane for the entire board. This ground plane should have a space between the analog and digital sections of the PCB. See page 95 of adv7181b.
  • In some cases, using separate ground planes is unavoidable. For those cases, it is recommended to place a single ground plane under the ADV7181B. The location of the split should be under the ADV7181B. For this case, it is even more important to place components wisely because the current loops are much longer (current takes the path of least resistance). An example of a current loop: power plane to ADV7181B to digital output trace to digital data receiver to digital ground plane to analog ground plane.
  • Analog Input Interface, Track lengths should be kept to a minimum, and 75 Ω trace impedances should be used when possible. Trace impedances other than 75 Ω also increase the chance of reflections.
  • PLL, Place the PLL loop filter components as close as possible to the ELPF pin. Do not place any digital or other high frequency traces near these components.
  • DIGITAL OUTPUTS (BOTH DATA AND CLOCKS), Try to minimize the trace length the digital outputs have to drive. Longer traces have higher capacitance, which requires more current, which causes more internal digital noise. Shorter traces reduce the possibility of reflections.

[edit] VGA Encoder

  • DIGITAL SIGNAL INTERCONNECT, Isolate the digital signal lines to the ADV7125 as much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power plane. Due to the high clock rates used, long clock lines to the ADV7125 should be avoided to minimize noise pickup. Connect any active pull-up termination resistors for the digital inputs to the regular PCB power plane (VCC) and not to the analog power plane.
  • ANALOG SIGNAL INTERCONNECT, Place the ADV7125 as close as possible to the output connectors, thus minimizing noise pickup and reflections due to impedance mismatch. The video output signals should overlay the ground plane and not the analog power plane, thereby maximizing the high frequency power supply rejection.

[edit] Audio Codec

  • The three inputs CD_GND, CD_L and CD_R act together as a quasi-differential stereo input with CD_GND providing AC common-mode feedback to reject ground noise. This can improve the input SNR for a stereo source with a good common ground but precision resistors may be needed in any external attenuators to achieve the necessary balance between the two channels.
  • There's a good application note AN-1528 which described a lot of errors that using LM4550B. Please see Figure 9 for searching errors and getting corrective answers in next page. What makes me interested in is "Very few of the errors prevent the circuit from workworking, but may impact the performance of the circuit depending on temperature, different production runs, etc." said by harry@ieee.org.

[edit] USB

  • High Speed USB Platform Design Guidelines
  • Match signal line traces (VP/VM, D+, D–) to 40ps, approximately 1/3 inch if possible. FR-4 PCB material propagation is about 150ps/inch, so to minimize skew try to keep VP/VM, D+/D– traces as short as possible.
  • For every signal line trace width (w), separate the signal lines by 1.5–2 widths. Place all other traces at >2w from all signal line traces.
  • Maintain the same number of vias on each differential trace, keeping traces approximately at same separation distance along the line.
  • Control signal line impedances to ±10%.
  • Keep RS as close to the IC as possible, with equal distance between RS and the IC for both D+ and D–.

[edit] Criteria for M1R4

  • keeping routes of Sdram as before
  • place all led at bottom side and close to related connectors. Be noticed that led vs board edge, at least FR4 would be translucent, allowing some light to pass at a steeper angle, see ref.
  • a) the microsd opening should not collide with the jtag-serial board, so either move the microsd aside a little, or the jtag-serial a little. b) the position of the jtag-serial connectors on m1, or the ethernet connector, should be such that a fully RECTANGULAR jtag-serial rc2 would fit c) the distance from the jtag-serial USB connector to the side wall(ethernet connector side) should be 1-2 mm more d) rearrangement of all top side part's references.
  • 1) let they layout people try to keep things (if that makes sense to them) 2) get a report of trace lengths. 3) see if anything sticks out as particularly bad. i wouldn't worry about a 501 mil difference anywhere. but, say, 1000 mil would be suspicious - by Werner, ref.

[edit] Link

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