Layout notes avt2 RC2 20091207

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´╗┐The following itemized numbers are based on last Layout_notes_avt2_RC2_20091116:

1, CON3, please see 1.jpg & 2.jpg, the illustration inside datasheet could be confused. Ours only has 3 pins (POS).MS24011P3R.pdf

2, please see 3.jpg & 4.jpg, you can put more GND "through vil" surrounding as close the GND pin of U2 & U3 as possible. In 4.jpg, there has used a dash line(means through GND layer), you can think and pick which one is the most shortest loop for current flow; so if we can put some vils to let in/out path for keeping equivalent current as shortest way. That would be better. Although i can surely know it can still work, the current goes its way. please also see item9.

3, in SilkS_Cmp layer for cpu die, please mark two cross which needed to position for cob vendor they write program to make position. please see 5.jpg

4, Please let XP/XN, YP/YN 4 pins out available. TP is ok enough.

5, SW1(usb boot switch) now is on the left front side. please see 7.jpg.

6, C72, C73 are now C0805 and ordered them already. No problems.

7, Due to few TPs cancelled, the space available; please see 6.jpg, if can fill GND copper into those black area, it would be great to shielding unnesscesary enduced noise a little bit from high digital signals.

8, PCB Text :QI_AVT2 REV.:RC2 in layer Silks_Cmp

9, Vils, if track width is 0.0118", then the both terminal side of each wire trace, the vils should bigger than track width; for examle:

       track width = 0.0315", through vil's diameter = 0.0118"
       then the length of the circumference (c) = 2 * 3.141592 * ( 0.0118 / 2 ) = 0.037"

since we are not sure normally the quality on processing vils on pcb maker, so the most safe way is to put 2 pcs of 0.0118" through vil (total equivalent width = 0.037 * 2 = 0.074) on the two ends of trace. Please see 8.jpg.

10, please see 9.jpg, can see section of "Bypass Capacitor Sequencing" of here, putting bypass capacitor between source and target, and close to target as possible.

11, +VBAT, keep the same width of trace. see 10.jpg.

12, N-000020, is the Q1 (S pin) or D2, the width should be wider and can put THREE 0.0197" through vils to connect another trace, please see 11.jpg.

13, Is it possible to let GND pin of Battery connector to be a solid trace not thermal one? And put 4 ~ 5 0.0118" vils close to GND pin as possible.

Category:LAYOUT NOTES

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