Layout notes avt2 RC2 20091116

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1, CON3 , I saw the pcb file , it has total 8 pins, must be only 3 pins and ground. do you want to use MS24011P3R(1.0mm pitch right angle smaller one) or MS24013R(1.25mm pitch right angle)? If we need use MS24011P3R, please see the MS24011P3R.pdf, please ignore I sent you the sample MS24011P3RA, it's wrong sample(180 degree). I'll request for the real one MS24011P3R).

2, I found that good you use always thermal pad (we called for cross solder paste), it's good for solder manually (MP stage), but you need be careful, Like U2 pin4 has thick trace but pin3 (L1.1)doesn't have the same width, it's not good. Current in needed be equal to keep current out based on width common ground. Same story on U3.3 <-> L2.1, please see EUP3406.pdf page 10.

3, N-000077 & N-000065 should be the same width as N-000065 & N-00068, others are not mentioned here i think should be modified like this. Main audio signal path should all keep the same width; but control signal like any MOSFET's Gate doesn't need. See C62_C59.jpg.

4, J3 on avt2_RC1 I made a mistake on placement, did you find? It should be shift to left a little bit to meet mechanical as well. Please see J3_shift_left_086mm.jpg.

5, I very agree and like you out U1.187 pin to be the bigger ground area, I should do like yours to expand copper; but one thing please must be changed back a little bit, because I asked Ingenic and cob vendor, the ground copper under cpu die should be add a little bit width than itself, for example , the jz4720 the die size is 4560um * 4960um, so they normally make a baseplate expandly to 5160um * 4760um by added plus 200um for each. Surrounding this area i think you still can use thermal copper pad.

6, I found you used 0.099mm(~3.89mil) width for each expanding bonding wire, it's differ from my 0.125mm(~4.92mil), I know now have many pcb maker they have accurate process can do above 3 mils trace but they just officially anouncement they can do it on some sample or small run, but for MP, their quality will hardly to maintain the same width with constant variance in every lot; maybe I produced some Moto phone in china before, but we still met a lot of defective rate or WIP in MP due to pcba maker's process; I am not sure how many lot of pcb your company made; if running a small quantity, they just picked the best one lot and send to you. But I have met many kind of this huge for MOTO project before, even the pcb maker they annoucement they can control the quality.So I used to choose a safe width around 5 mils for trace, also I arranged a 0.15mm(5.9mil)/0.12mm(4.7mil)/0.15mm(5.9mil) for sectorial shape in:

 pcb layout plan:
 --> approximately -->   6 mil width pad / 5 mil width gap / 6 mil width pad and so on...  
 after pcb maker's etching process, they will become variably as:
 --> approximately -->   5               / 6               / 5
 so this 5mil pad will be coonected to all thin control signal trace ( smaller than 4.9 mil )
 now yours is :
 --> approximately -->   4.92 mil width pad / 3.38 mil width gap / 4.92 mil width pad   
 after pcb maker's etching process, they will become variably as:
 --> approximately -->   3.9                / 4.3                / 3.9
 so this 3.9mil pad will be connected to all thin control signal trace ( smaller than 3.89 mil )

why I designed like this:

a) the width of golden wire is 0.7mil here in Taiwan cob vendor but China has 0.8mil aluminum capability. So the most safe space is more bigger than 2 times of 0.8mil = 1.6 mil (40.65um) which is a bit smaller than die pad only. See the smallest pad on cpu die is 50*50um only, so chose 0.7 mil is more safe and also i can only find here Taipei they have; but for design a reference board , maybe in the future, some one will use our design and make A LOT quantity hopefully but China's COB we're now still hard to find a suitable for our few scale. b) the example small distance between CPU pad 73 and 74 is 76um only, so the explosion sectorially from cpu die to bonding outside pad, should be carefull. c) the Ben- NanoNote our OEM they don't use all 186 pins of jz4720, so they only layout for 165 pins bonding wires for the cob pad as a square shape. d) at SilkS_Cmp layer for cpu die, please mark two cross which needed to position for cob vendor they write program to make position. cpu_die_position_point.jpg

7, you cancelled XP/XN, YP/YN? touch screen? I left them becuase of someone is crazy he wants to study touch screen future. I think you have good reason, right?

8, R39= 2.2K/5%, sorry the schematic is 22k, please change schematic to 2.2K/5%, avt2_RC1 is 2.2K/5%.

9, R40 & R41 is 100/5% in schematic but I found I make mistakes again, in avt2_RC1 I used 1k/5%, but it still works well due to volatage divided, so bom I changed it correct into 100/5% now.

10, R60 100K/5% R0603 must move to somewhere, otherwise the battery case will interfere it. If you agree, we can change this package 0603 into 0402.

11, SW1 not changed to P/N: MK-12C02-PB, see MK-12C02-PB.pdf.

12, C59, C62 is 100uF/4V in qi_lb60 (Ben-Nanonote) they used A-case in huge quantity, here I can not get, so I changed to 100uF/6.3V B-case.

13, C72, C73 are C0805, I am requesting the parts.

14, I cann't figure out the footprint of key Key.jpg,

15, shift uSD a little bit

16, add 0.1uF/16V /C0402 between U6 pin1 and pin2


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