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[edit] AC'97/I2S CODEC

The processor jz4740 contains a protocol defined by Philips Semiconductor called AIC, which consists of buffers, status registers, control registers, serializers, and counters for transferring digital audio between the Jz4740 processor system memory and an internal I2S CODEC, an external AC'97 or I2S CODEC, as shown below:

Figure 1. Jz4740 AIC Interface to the Internal I2S CODEC and External AC’97 CODEC Diagram

For playback of digitized audio, the AIC retrieves digitized audio samples from system memory and sends them to a CODEC through the serial connection, this communication is achieved through two formats supported by AIC: AC-link format or I2S/MSB format. The internal or external digital-to-analog converter in the CODEC then converts the audio samples into an analog audio waveform. The audio sample data can be stored to and retrieved from system memory.

Here are the signs when working with the I2S/MSB CODEC format in master mode and slave mode:

Figure 2. Jz4740 Interface to an External Master Mode I2S CODEC Diagram
Figure 3. Jz4740 Interface to an External Slave Mode I2S CODEC Diagram

[edit] Signal Descriptions

There are all 6 pins used to connect between AIC (located inside the processor) and an external audio CODEC device.

[edit] RESET# / SYS_CLK Pin (Output signal for the two formats)

RESET#: Is simply a reset signal. The CODEC’s registers are reset when this RESET# is active-low. This pin is useful only in AC-link format. If AIC is disabled, it retains the high.

SYS_CLK: This pin is useful only in I2S/MSB-justified format to supply system clock to CODEC. It generates a frequency between approximately 2.048 MHz and 24.576 MHz. This frequency can be 256, 384, 512 and etc. times of the audio sampling frequency. Or it can be set to a wanted frequency. If AIC is disabled, it retains the high.

[edit] BIT_CLK Pin (Input signal for AC-link format and input/output signal for I2S/MSB format)

BIT_CLK is the serial data bit rate clock, at which AC97/I2S data moves between the CODEC and the processor. One bit of the serial data is transmitted or received each BIT_CLK period. It is fixed to 12.288 MHz in AC-link format. In I2S and MSB-justified format it inputs from the CODEC in slave mode and outputs to CODEC in master mode.

[edit] SYNC Pin (Output signal for AC-link format and input/output signal for I2S/MSB format)

In AC-link format, SYNC provides frame synchronization, fixed to 48kHz, by specifying beginning of an audio sample frame and outputs to CODEC. In I2S/MSB-Justified formats, SYNC is used to indicate left- or right-channel sample data and toggled in sample rate frequency. It outputs to CODEC in master mode and inputs from CODEC in slave mode.

[edit] SDATA_OUT Pin (Output signal for the two formats)

SDATA_OUT is AIC output data pin, which outputs serial audio data or data of AC97 CODEC register control to an external audio CODEC device. If AIC is disabled, it retains the low.

[edit] SDATA_IN Pin (Intput signal for the two formats)

SDATA_IN is AIC inputs data pin, which inputs serial audio data or data of AC97 CODEC register status from an external audio CODEC device. If AIC is disabled, its state is undefined.


Audio data is MSB adjusted, regardless of 8, 16, 18, 20, 24 bits sample size. When a 24-bits sample is transmitted, the LSB 4-bits are truncated. When try to record 24-bits sample, 4-bits of 0 are appended in LSB.

Figure 2. AC-link audio frame format


The BIT_CLK supplies the serial audio bit rate, the basis for the external CODEC bit-sampling logic. Its frequency is 64 times the audio sampling frequency. Divided by 64, the resulting 8 kHz to 48 kHz or even higher signal signifies timing for left and right serial data samples passing on the serial data paths. This left/right signal is sent to the CODEC on the SYNC pin. Each phase of the left/right signal is accompanied by one serial audio data sample on the data pins SDATA_IN and SDATA_OUT.

Figure 3. Jz4740 I2S data format

Data is sampled on the rising edge of the BIT_CLK and data is sent out on the falling edge of the BIT_CLK.

Data is transmitted and received in frames of 64 BIT_CLK cycles. Each frame consists of a left sample and a right sample. Each sample holds 8, 16, 18, 20 or 24 bits of valid data. The LSB other bits of each sample is padded with zeroes.

  • In the normal I2S mode, the SYNC is low for the left sample and high for the right sample. Also, the MSB of each data sample lags behind the SYNC edges by one BIT_CLK cycle.
  • In the MSB-justified mode, the SYNC is high for the left sample and low for the right sample. Also, the MSB of each data sample is aligned with the SYNC edges.

When use with the internal CODEC, the BIT_CLK and SYNC signals are provided by the internal CODEC from the 12MHz clock.


The files required to make possible the serial connection for digital audio I2S are located in openwrt-xburst/build_dir/linux-xburst_qi_lb60/linux-

  1. Makefile
  2. core.c
  3. pcm.c
  4. interface.h
  5. i2sbus.h
  6. control.c

The Makefile contains the necessary to realize the make function

  1. obj-$(CONFIG_SND_AOA_SOUNDBUS_I2S) += snd-aoa-i2sbus.o 
  2. snd-aoa-i2sbus-objs := core.o pcm.o control.

[edit] core.c

This file contains the i2sbus driver. In this code are defined the next functions:

  • alloc_dbdma_descriptor_ring
  • free_dbdma_descriptor_ring
  • i2sbus_release_dev
  • irqreturn_t
  • i2sbus_get_and_fixup_rsrc
  • i2sbus_add_dev
  • i2sbus_probe
  • i2sbus_remove
  • i2sbus_suspend
  • i2sbus_resume
  • i2sbus_shutdown
  • __init soundbus_i2sbus_init
  • __exit soundbus_i2sbus_exit

The functions uses the next part of code to define the i2sbus device:

  1. struct i2sbus_dev { 
  2. struct soundbus_dev sound;  
  3. struct macio_dev *macio; 
  4. struct i2sbus_control *control; 
  5. volatile struct i2s_interface_regs __iomem *intfregs;

Since line 6 the code defines the resources required

  1. struct resource resources[3]; 
  2. struct resource *allocated_resource[3]; 
  3. int interrupts[3]; 
  4. char rnames[3][32]; 
  6. /* info about currently active substreams */ 
  7. struct pcm_info out, in; 
  8. snd_pcm_format_t format; 
  9. unsigned int rate; 
  11. /* list for a single controller */ 
  12. struct list_head item; 
  13. /* number of bus on controller */ 
  14. int bus_number; 
  15. /* for use by control layer */ 
  16. struct pmf_function *enable, 
  17. *cell_enable, 
  18. *cell_disable, 
  19. *clock_enable, 
  20. *clock_disable; 
  22. /* locks */ 
  23. /* spinlock for low-level interrupt locking */ 
  24. spinlock_t low_lock; 
  25. /* mutex for high-level consistency */ 
  26. struct mutex lock; 
  27. };

In the functions we mentioned we have functions like alloc_dbdma_descriptor_ring and free_dbdma_descriptor_ring. This functions defines the requiered parameters to realize the DMA. The device has DBDMA hardware, what it means descriptor-based DMA. It allows the device to have direct access to the memory to read or to write independently of the central processing unit. Its easy to imagine because the interaction between the serial port and the memory should be in a short time to play the stored audio like in real time, what makes it impossible the participation of the central processing unit.

There is a function called irqreturn_t used to handle the interruptions in the device. The function i2sbus_release_dev is used to initialize the device. On the other hand there are function like i2sbus_add_dev to add the device, or i2sbus_probe to test the compatibility with I2S, or i2sbus_remove to remove the device after you finish using the serial port.

The code shut down the device using the function i2sbus_shutdown and the last two items are modules used to initialize and to exit the sound bus.

[edit] pcm.c

The Pulse Codification Modulation is the digital representation of an analog signal where the magnitude of the signal is sampled regularly at uniform intervals. This kind of codification is used in I2S so it is necessary to include a driver with the required pcm routines.

[edit] Interface.h

This header file contains the interface register definitions. It defines the bus control registers, the interrupt registers and the serial format registers.

The interrupt registers are just a bitfield with interrupt enable and pending bits.

On the other hand the serial format register has an interesting structure. It contains:

  1. Clock source
  2. MClk divisor
  3. SClk divisor
  4. SClk master flag
  5. serial format that includes: sony, i2s, 64x, 32x, dav, sílabs.
  6. External sample frequency interrupt
  7. external sample frequency

The MClk is known as the system clock. This clock drives the whole codec. This signal is derived by taking only every 'divisor' tick of the clock. And the SClk is the clock that drives the i2s wire bus specifically. The definition of this signal is derived from the MClk because it takes only every 'divisor' tick of MClk. In this file are defined too the external sample frequency and the external sample frequency of interruptions.

[edit] control.c

In this file are defined the bus control routines required to realize I2S interface. The functions defined in this file are used in core.c.

The functions in this header:

  1. i2sbus_control_init
  2. i2sbus_control_destroy
  3. i2sbus_control_add_dev
  4. i2sbus_control_remove_dev
  5. i2sbus_control_enable
  6. i2sbus_control_cell
  7. i2sbus_control_clock

With these functions the driver core.c can realize the required activities to mantain the comunication through I2S interface.

[edit] I2sbus.h

This header contains private definitions about I2S interface. It shows the order of the pcm specific functions and the order of the control specific functions according to the serial interface comunication.

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