Hardware Hello World

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NOTE, SAKC has been renamed SIE. So, some places SAKC is referred to as SAKC.

Caution: While you are going to use V2 version of SIE, make sure DC adapter DO NOT plug-in while you are to use USB cable, and J18 has a mini-jumper used to short it. J18 is to let you transfer USB cable +5V to SIE's supplies. Then you can connect Host PC with SIE by usb cable. DO NOT plug-in usb cable and DC adapter at the same time. Otherwise you may damage your host device, SIE or adapter.


[edit] Hello World Application Hardware

The SIE FPGA has no connections with a display device such as an LCD, so our basic application will be a blink, that is, a LED that turns on and off periodically, this is sufficient to verify the correct operation of the FPGA and processor configuration channel.

The quickest way to implement this blink is using a counter, each output bit of this counter performs the division by powers of two of the clock signal. The following code assigns the signal led the value of counter [24], which provides the clock signal divided by 2 ^ 25 (33,554,432).

`timescale 1ns / 1ps
  module blink(clk, reset, led);
  parameter     B = (7);
  input            clk, reset;
  output           led;
  reg [24:0] counter;
  always @(posedge clk) begin
    if (reset)
      counter <= {25{1'b0}};
      counter <= counter + 1;
  assign led = counter[24];

Here you can download the source code of this application. In order to generate the FPGA configuration is necessary.

[edit] Configuring a USB Network Interface with SIE

SIE must connect to your computer using the USB cable provided with the command dmesg you'll get this message:

$ dmesg
   usb0: register 'cdc_subset' at usb-0000:00:1d.0-1.3, Linux Device, ee:a9:fe:4d:b6:54

Now you must configure the usb0 network interface:

$ sudo ifconfig usb0 up

SIE initially not assigned a password for root, which is required for the transfer of files, to assign a password to the root of SIE establish a telnet session:

$ telnet

Which will provide a console where you can run the command:

$ passwd

Additionally, we must create a directory stored a configuration file:

$ mkdir /usr/share/xc3sprog'

[edit] Transferring files to SIE

Once the connection is established and assigned a password to root user can establish a session scp to transfer files to SIE

$  scp xc3sprog root@ # copy xc3sprog to /usr/bin
$  scp devlist.txt root@ # copy devlist.txt to /usr/share/xc3sprog
$  scp blink.bit root@        # copy blink.bit to /root

[edit] Make a ssh connection with SIE

$ ssh -l root #This is to make a ssh connection with SIE.
root@'s password:  #type ENTER key

The following msg will be shown after couple seconds.

BusyBox v1.15.3 (2010-04-09 03:19:07 CEST) built-in shell (ash)
Enter 'help' for a list of built-in commands.
 _______                     ________        __
|       |.-----.-----.-----.|  |  |  |.----.|  |_
|   -   ||  _  |  -__|     ||  |  |  ||   _||   _|
|_______||   __|_____|__|__||________||__|  |____|
         |__| W I R E L E S S   F R E E D O M
KAMIKAZE (bleeding edge, r20653) ------------------
 * 10 oz Vodka       Shake well with ice and strain
 * 10 oz Triple sec  mixture into 10 shot glasses.
 * 10 oz lime juice  Salute!


[edit] Some usefull Spartan-3E programs to test SIE's IOs

Under binaries folder, there are some usefull programs. There's an utility for configure the FPGA called xc3sprog.

[edit] Ex1. blinking LED D5

Use xc3sprog to configure the FPGA with the configuration file blink.bit to let LED D5 blinking.

root@BenNanoNote:~/binaries# xc3sprog ./blink.bit
 Release 0.5 
 Device with ID=41c22093 found

Then the D5 which connected to fpga is blinking. If this works, means the configuration channel between FPGA and processor works well. If you run the configure file again, the D5 will off during Programming stage.

[edit] Ex2. bus connection test between jz4725 and FPGA

Test the connection between processor's data, address & CTRL buses and FPGA. You need this Ex2 and Ex3 to complete connection. So first use xc3sprog to configure FPGA.

root@BenNanoNote:~/binaries# xc3sprog ./sram_bus.bit

After configuring, the D5 is blinking again. If you press PB2 (reset fpga) the led stop to blink if you release PB2 the led blink again.

[edit] Ex3. transferring byte data between jz4725 and FPGA

Before doing this exercise, you must run Ex2. first, so now if we can send byte data into fpga and read back.

root@BenNanoNote:~/binaries# ./jz_init_sram
Configuring CS2 8 bits 
Reading Memory..
 0 = 0
 1 = 1
 2 = 2
 FC = FC
 FD = FD
 FE = FE

With this, can know data connection well or not.

[edit] Ex4. serial connection between jz4725 and FPGA

There are J6 & J7 headers on SIE board, RX1 & TX1 from processor, and RX2 & TX2 from FPGA; so we can make connections directly as below:

RX2(FPGA) <<== TX1 (jz4725)
TX2 (FPGA) ==>> RX1 (jz4725)

so you can load a mips processor on FPGA to finish this exercise. Before doing this, you need to make sure that there's no process run on FPGA, also need to kill sgen if it's running:

root@BenNanoNote:~/binaries# ps -fea #check what process is running
645 root      1064 S    /usr/bin/sgen -f 1000 
646 root     20588 S    /root/binaries/ADC -qws -nomouse 
root@BenNanoNote:~/binaries# kill -9 645 646 #kill sgen and ADC

There is an application to enable the reception in processor side. NanoNote by default blocks the serial port, so we need the enable it.

root@BenNanoNote:~/binaries# ./enable_rx

Now we can load a mips processor on FPGA:

root@BenNanoNote:~/binaries# xc3sprog ./plasma.bit #with this application you load a mips processor on FPGA

After loading, the LED D5 is ON when you push and hold PB2 tact switch. Now we can open an minicom to check if the serial connection is good.

root@BenNanoNote:~/binaries# minicom -s #set the serial port /dev/ttyS0 at baud rate 57600, N8, 1, Hardware Flow Control : No, Software Flow Control : No

For more details of using minicom, please check http://alioth.debian.org/projects/minicom/. Make sure you saved the setting. Now,

root@BenNanoNote:~/binaries# minicom

If SIE runs correctly with making connections on J6 & J7, you should can see a Menu in minicom:

Waiting for binary image linked at 0x10000000        
Other Menu Options:                                  
1. Memory read word
2. Memory write word
3. Memory read byte
4. Memory write byte
5. Jump to address
6. Raw memory read
7. Raw memory write
8. Checksum
9. Dump
F. Copy 128KB from DDR to flash

Then if you press "1" and "ENTER", the menu ask you:

Address in hex> 0 #type "0" then will show as below
Address = 00000000
3C1C0001                #now you just implement a serial connection between jz4725 and FPGA

The file plasma.bit displays a menu. So the FPGA sent this menu using its TX2 line and the processor received this menu via RX1 and displayed it on minicom. So when you type 1, the processor sends those characters to FPGA by using TX1 and the FPGA receives it on RX2. So you can write specified address with word data then read back to check if word data is correct. With this, we completely checked both serial channels at the same time.

[edit] Ex5. ADC test with scope views

SIE have one ADC converter on board, you can use jz4725 to generate a sinewave then sends it into ADC's input and shows a real waveform on screen. So like Ex4. pls make sure killed necessary processes related to sgen and ADC. After confirmed, make sure U11's pin-14 ADC_VREF thus is J19's pin 30 connected to specified DC reference. Here you can directly make a connection between pin 30 and pin 29 (3.3V). Also making two connections as below:

J16 pin3(R-HPO) <---> J19 pin37(ANALOG0) , means let jz4725's right headphone out goes into U11(TLV1548)'s ANALOG0, CH1(BLUE)
J16 pin4(L-HPO) <---> J19 pin38(ANALOG1) , means let jz4725's left headphone out goes into U11(TLV1548)'s ANALOG1, CH2(RED)

Then enter:

root@BenNanoNote:~/binaries# /usr/bin/xc3sprog /root/binaries/ADC.bit
Release 0.5 
Device with ID=41c22093 found
root@BenNanoNote:~/binaries# /usr/bin/sgen -f 1000 &
root@BenNanoNote:~/binaries# /root/binaries/ADC -qws -nomouse &
root@BenNanoNote:~/binaries# ADC: Configuring CS2 8 bits and 0 WS: 00000000
ADC in Fast Convertion Mode (10us) and Fs=9.8KHz (Min)
INIT TEST1: Autoselft {(Vref+) - (Vref-)}/2 -> Return 0x0200 
INIT TEST2: Autoselft (Vref-) -> Return 0x0000 
INIT TEST3: Autoselft (Vref+) -> Return 0x03FF 
TESTS complete
Taking 120 samples by channel at Fs=99KHz (trigger=50ms)

So now you should can see two sine waveforms in RED and BLUE color on screen.

[edit] Some usefull program to test SIE's jz4725

root@BenNanoNote:~/binaries# ./jz_test_gpio

This is to blink D6 from jz4725 processor

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