GPS Free Stack/Data Acquisition

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[edit] Interfacing

Due Ben nanonote Xburst chip is not capable of support more than 2.4Mpbs of throughput for serial data, according for some tests made by Werner Almesberger (http://lists.en.qi-hardware.com/pipermail/discussion/2010-November/006025.html). The SIE board will be used initially to deploy in the FPGA the logic to capture the raw data from SiGE EVB. Later a serial to parallel approach in CPLD may be tested in the ben side. For the FPGA <-> Xburst SoC interconnection, a SDIO like bus will be used.

Current Wiring Status:

[edit] SIE <- SiGE EVB

   SE4162T-EK1 EVB                                           SIE                    FPGA
  J4 Pin 1 VBAT     .................................... J19 Pin 28 3V3
  J4 Pin 3  SYNC    ------------------------------------ J19 Pin 24 DIG 22         Pin 33
  J4 Pin 4  DATA    .................................... J19 Pin 22 DIG 20         Pin 35
  J4 Pin 5  CLK_OUT ------------------------------------ J19 Pin 20 DIG 18         Pin 40
  J4 Pin 8  GND     .................................... J19 Pin 26 GND
  J5 ANT  (to active GPS External Antenna)

SiGE EVB Jumper positions:

 J1 2<->3 Fit
 J9 1<->2 FIT
 R4 0 = 0R

This setup allow the use of the on-board regulator (wich is not the internal LDO from SiGE chip).

Optional Debug Signals

  J4 Pin 10 Vdd  (Expected 2V9~ in normal operation)
  J4 Pin ANT_DET (Expected 3V3~ When External ANT connected)

[edit] Xburst <-> FPGA

FPGA in SIE share data and address bus with SDRAM, SIE Examples suggest a map FPGA as ram by help of EMC in Xbusrt. Then a 2048bit sram block is implemented in the fpga (in read-first write mode) arranged with a counter in order to behave like a ring buffer.

[edit] SE4162

Data output format: Serial 4-bit baseband I/Q pulse sync data

2.048 Msps 4-bit I/Q interleaved, pulse sync 
               __   __   __   __   __   __
DATA         _/SI\_/MI\_/SQ\_/MQ\_/SI\_/MI\
              \__/ \__/ \__/ \__/ \__/ \__/

               __                  __  
SYNC         _/  \________________/  \_____

               __   __   __   __   __   __
CLK_OUT      _/  \_/  \_/  \_/  \_/  \_/  \
(8.192 Mhz)          Positive Edge

Frame Structure: Repeating sequence of SI MI SQ MQ Active high SYNC pulse aligns with SI Sample Rate: 2.048 MSPS

Sample clock output: 8.192 MHz

GPS data and clock load: 15pF max (Nanonote pin is about 5pf)

IF Filter Centre Freq: 2.556 MHz

IF Filter BW: 2.2 MHz

TCXO reference frequency: 16.384 MHz

Tolerance: ±1.5 ppm (Set tolerance and 2 reflows)

Temperature (-30 to +85° ±0.5 ppm)

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