Boot Modes

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NAND Flash boot

When the file system is initialized through NAND Flash, the boot program configures EMC and GPIO ports, according to the first byte information. The first thing it does is to read the first NAND byte in order to know if it is 16-bits or 8-bits wide, and if it is 2 or 3 page cycles. When bit’s [7:4] information from the first byte is 0, NAND is 16-bits wide. otherwise it is 8-bits wide. Then, bit’s [3:0] from the first byte are read so the page cycles can be determined, if these are 0, it has 2 page cycles, if not, it has 3. In this case, NanoNote uses one NAND flash with a 16-bits communication, although it only uses 8 bits. After that, it loads 8Kb from NAND to the internal SRAM and jump to the internal SRAM until it moves 4 bytes.

The boot program is capable of loading 2 data area of the NAND flash to the internal SRAM. One is the normal area, in which it loads 8Kb from NAND flash from 0 address, and the other one is the backup area, where this boot program loads 8Kb of data too, but it starts from 0x2000 address. The followed Data flow is presented in the next image. After reset, the first byte of the NAND is read, and then the normal area of the NAND is read from address 0 through the [Reed-Solomon [ECC]], the ECC problems are checked, if there is no problems or if those are corrected, then the boot program jumps to the internal SRAM and moves 4 bytes. If there are problems that cannot be corrected, then the backup area of the NAND is read using Reed-Solomon ECC, from 0x20000 address. As we said before, if there are not ECC errors or those are corrected, it jumps to the internal RAM and moves 4 bytes. If those errors cannot be corrected, then it tries to initialize from the NOR flash, but as Nano does not have this kind of memory, that cannot be done.

Every time that the boot program starts reading a page, it checks if data is correct. If yes, it reads the internal SRAM page, If not, it finish reading and jumps to the SRAM and moves 4 bytes. The boot program is going to decide if this page is valid according to the third, fourth and fifth byte from its reserved area. If one of these three bytes is 0, data is valid, if not, data is not valid. The boot program enables hardware RS ECC when it reads the NAND flash data. When the 512-byte is read, it compares the ECC stored with the calculated one. They both have 9 bytes per every 512 data bytes. The ninth stored byte starts from the seventh byte of each page reserved area.

Nand Boot Flow Diagram

USB boot

When the boot is chosen from the USB (when BOOT_SEL is [1:0]), there is an advantage over the other modes, because data transmition takes less time, about two minutes. After these pins are chosen, internal boot ROM waits USB host requirements, until it download the boot program from the USB port and loads it to the internal SRAM, and then, jump to the SRAM in order to start running the program.

Boot program can be done through two different transference ways, full-speed done at 12MHz, and high-speed, at 480MHz. next you can see the two types of transference.


Communication flow between host and JZ4720 is shown next, where you can see in a general way the sending and the reception of info.

Comunication host-device USB

USB host programs the next 6 vendor-request VR_GET_CPU_INFO (0x00), VR_SET_DATA_ADDRESS (0x01), VR_SET_DATA_LENGTH (0x02), VR_FLUSH_CACHES (0x03), VR_PROGRAM_START1 (0x04) y VR_PROGRAM_START2 (0x05), through the endpoint control, which allow to download/upload information to/from device, and then jump to an address when the program transferred through Bulk IN o Bluk OUT endpoint is executed.

When USB is connected and the host recognizes it, it starts the device enumeration. When this is ended, the first vendor request can be sent VR_GET_CPU_INFO (0x00), which is, like its name says, the one in charge of consulting the CPU information. Then, if you want to upload/download a program to/from the device, two vendor request are sent,first VR_SET_DATA_ADDRESS (0x01) y VR_SET_DATA_LENGTH (0x02) to indicate the data transfer byte address and size that are going to be done, Which can be made through Bulk-in/Bulk-out endpoint. When the first part has finished transferring all data to the device, the next vendor request Is sent, VR_PROGRAM_START1 (0x04) in order to CPU to do the program, which cannot be bigger than 16Kb and is used to initialize target board’s GPIO and SDRAM. When the first part is done, it returns to the internal boot program jumping to the $31 register. Now the user can download a new program to the SDRAM from the target board as in the first stage, and send another vendor request again VR_FLUSH_CACHES (0x03) and VR_PROGRAM_START2 so the CPU can run the program. The boot through USB flow is shown next.

Secuence usb boot
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