Audio IN OUT

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NanoNote audio circuit is shown in the next image. there you can see the microphone conections. Earphone and speaker are connected with the analogue module of the internal Codec.(yellow Blocks represent internal processor Blocks)

Audio Circuit.png

JZ4720, JZ4740 and JZ4725 Processors support direct earphones to amplifier connection, so as the direct microphone connection. This chip has a BG amplifier at microphone input, so it is not necessary to amplify its output signal. Besides, MICBIAS pin provides the bias voltage so that microphone can work. [1]. Modifying SW1 y SW2 switches state:

  • SW1 closed: take audio signals from microphone, or LINEIN_L and LINEIN_R input signals (Not available in Nano) to ouput directly, and mix them with signals from the Digital/Analogue converters (DAC) (SW2 closed) or not (SW2 open) depending on SW2 state.
  • SW1 opened & SW2 closed: DAC ouput is connected to output circuit, which allows the reproduction of the DAC info, when you are reproducing a music file for example.
  • SW1 $ SW2 opened: No signal is connected to output circuit.

Microphones,LINEIN_L and LINEIN_R' inputs go to ADC(analogue to digital converter) directly, which allows recordings to be processed or reproduced later. If you want to work with LINEIN_L and LINEIN_R output signals, microphone gain must be 0 (CDCCR2.MICBG = 0), otherwise, the signal coming from this line is going to be mixed with input signal.


[edit] Earphones

As we said before, JZ4720 allows direct connection from the earphones to the output pins. This makes the circuit less complex so that costs can be reduced. Next image shows that one capacitor (C59 / C62) is connected in a serial way to each channel in order to cut DC, One N-type MOSFET (Q9 / Q10) as a switch and one resistor (R37 / R38) that brings control of output circuit current in case of a short-circuit from earphones connector. R40 and R41 resistors are used to show the state of earphones(if it is present or not). POP signal is in charge of the control of Q9 and Q10 "switches".

Audio Out.png

When POP has a high analogue value (3.3V in this case), Q9 and Q10 transistors Gate-source voltage is 3.3V. As the required value of saturation is 1.3V, these transistors go from satured region (closed switch) so that the circuit changes to: Audio POP HI.png

On the other hand, if we change POP to a Low value (0V), Q9 and Q10 transistors Gate-source voltage is 0V, so, these transistors work as an open switch. The circuit changes to: Audio POP LOW.png

when the earphone is connected (and we close Q9 and Q10 “switches”), the circuit changes to the one on the next image, where we can see that the signal going to earphones has only one AC component, because DC component was cut by C59 / C63 capacitors.

Headphone in.png

Now, When the earphone is removed (you can see the circuit on the next image), the voltage value changes in the node called AMPIN, it goes from 3.3V (as you can see in the last image) to one value close to 0.

Headphone out.png

[edit] Speaker

Speaker is controlled by a two-channel power amplifier that can be enabled using an a uthorizer (“CE” , pin 7). If audio amplifier is disabled, its power consumption is 0, so battery charge time rises because there is a lower power consumption.

Obviously, When the earphone is connected, it must be disabled in order to do not reproduce sound in both outputs. Equivalent circuit of this situation is shown in the next image. The state of “CE” signal, coming from the amplifier, is determined by the Q6 (P-channel MOSFET) transistor state. Its Gate-Source voltage is 3.3V because R36 and R42 give 3.3V and 0V to Gate and Source respectively; So, transistor is now in cut-off mode, and we can erase Q6 of this circuit. With this , “CE” signal from the amplifier takes a 0V value so the circuit is disabled.

Audio SP.png

When the earphone is removed, is necessary the amplifier to be able of being activated whenever the user wants. Next image shows the equivalent circuit after the earphone is removed. Again,the value of “CE” , the pin of the amplifier, depends on the Q6 transistor state (who works as a switch). In this case, Q6 gate voltage is VAMPIN, which can be calculated from the resistance division coming from R36 and (R40 + R37) with (R38 + R41) shunt. (next image shows the equivalent circuit )

Audio SP WOHP.png

Source voltage comes from “AMPEN” signal value. If “AMPEN” has a high logic value (3.3V), Q6 Gate-Source voltage is VGate(0) - VSource(VAMPEN) = -3.3V. This makes Q6 transistor to go on a saturation state, and “CE” pin value is 3.3V; if “AMPEN” has a low logic state, Q6 Gate-Source voltage is 0V, so Q6 is in cut-off state (opened switch) and “CE” pin voltage is 0V.

Audio SP WOHP2.png

[edit] Microphone

This is a very simple circuit, because processor has the necessary support to feed and amplify the microphone signal. This is shown next:


[edit] CONTROL

POP and AMPEN signals allow the output control going to earphones and amplifier respectively. These are managed by two GPIO (general in-out pin) as we can see on [Link página GPIOs]. Each Processor’s GPIO enable a pull-up or a pull-down, in this reset state, GPIOs are declared as inputs and pull-on is activated, so when Nano is initialized, “POP”and “AMPEN” still in high logic value, which enables earphones and amplifier.

You can find this pin declaration in arch/mips/include/asm/mach-jz4740/board-qi_lb60.h.

  1. #define GPIO_AMP_EN             JZ_GPIO_PORTD(4)  // AMPEN
  2. #define GPIO_AUDIO_POP          JZ_GPIO_PORTB(29) // POP

Estos pines son declarados como salidas e inicializados en el archivo arch/mips/jz4740/board-qi_lb60.c

This pins are declared as outputs and initialized in the next file: arch/mips/jz4740/board-qi_lb60.c

  1. static void __init board_gpio_setup(void)
  2. {
  3. ...
  4.   __gpio_as_output(GPIO_AMP_EN);
  5.   __gpio_set_pin(GPIO_AMP_EN);
  6.   __gpio_as_output(GPIO_AUDIO_POP);
  7.   __gpio_set_pin(GPIO_AUDIO_POP);
  8. ...
  9. }

Functions related to GPIOs management are declared in arch/mips/include/asm/mach-jz4740/ops.h file.

  1. ...
  2. #define __gpio_get_pin(n)			\
  3. ({						\
  4. 	unsigned int p, o, v;			\
  5. 	p = (n) / 32;				\
  6. 	o = (n) % 32;				\
  7. 	if (__gpio_get_port(p) & (1 << o))	\
  8. 		v = 1;				\
  9. 	else					\
  10. 		v = 0;				\
  11. 	v;					\
  12. })
  14. #define __gpio_get_port(p)	(REG_GPIO_PXPIN(p))
  16. #define __gpio_set_pin(n)			\
  17. do {						\
  18. 	unsigned int p, o;			\
  19. 	p = (n) / 32;				\
  20. 	o = (n) % 32;				\
  21. 	REG_GPIO_PXDATS(p) = (1 << o);		\
  22. } while (0)
  24. #define __gpio_clear_pin(n)			\
  25. do {						\
  26. 	unsigned int p, o;			\
  27. 	p = (n) / 32;				\
  28. 	o = (n) % 32;				\
  29. 	REG_GPIO_PXDATC(p) = (1 << o);		\
  30. } while (0)
  31. ...
  32. #define __gpio_as_output(n)			\
  33. do {						\
  34. 	unsigned int p, o;			\
  35. 	p = (n) / 32;				\
  36. 	o = (n) % 32;				\
  37. 	__gpio_port_as_output(p, o);		\
  38. } while (0)
  40. #define __gpio_as_input(n)			\
  41. do {						\
  42. 	unsigned int p, o;			\
  43. 	p = (n) / 32;				\
  44. 	o = (n) % 32;				\
  45. 	__gpio_port_as_input(p, o);		\
  46. } while (0)
  48. #define __gpio_port_as_output(p, o)		\
  49. do {						\
  50.     REG_GPIO_PXFUNC(p) = (1 << (o));		\
  51.     REG_GPIO_PXSELC(p) = (1 << (o));		\
  52.     REG_GPIO_PXDIRS(p) = (1 << (o));		\
  53. } while (0)
  55. #define __gpio_port_as_input(p, o)		\
  56. do {						\
  57.     REG_GPIO_PXFUNC(p) = (1 << (o));		\
  58.     REG_GPIO_PXSELC(p) = (1 << (o));		\
  59.     REG_GPIO_PXDIRC(p) = (1 << (o));		\
  60. } while (0)

Where (arch/mips/include/asm/mach-jz4740/regs.h):

  1. ...
  2. #define REG_GPIO_PXDATC(n)	REG32(GPIO_PXDATC((n)))
  3. #define GPIO_PXDATC(n)	       (GPIO_BASE + (0x18 + (n)*0x100)) /* Port Data Clear Register */
  5. #define REG_GPIO_PXFUNC(n)	REG32(GPIO_PXFUNC((n)))
  6. #define GPIO_PXFUNC(n)	(GPIO_BASE + (0x48 + (n)*0x100)) /* Function Clear Register */
  8. #define REG_GPIO_PXSELC(n)	REG32(GPIO_PXSELC((n)))
  9. #define GPIO_PXSELC(n)	(GPIO_BASE + (0x58 + (n)*0x100)) /* Select Clear Register */
  11. #define REG_GPIO_PXDIRC(n)	REG32(GPIO_PXDIRC((n)))
  12. #define GPIO_PXDIRC(n)	(GPIO_BASE + (0x68 + (n)*0x100)) /* Direction Clear Register */
  14. #define REG_GPIO_PXDIRS(n)	REG32(GPIO_PXDIRS((n)))
  15. #define GPIO_PXDIRS(n)	(GPIO_BASE + (0x64 + (n)*0x100)) /* Direction Set Register */

We can now find the steps that must be followed to configure a GPIO as an input or output:

1. Define pin function with PXFUN register, if PXFUN =0, this can be used as GPIO or interruption input. If PXFUN =1, this pin is configured to do another function if it is related to one peripherical.

2. Define PXSELX register. When PXFUN =0, if PXSELX=0 it is used as a GPIO, if PXSELX =1 it is used as an interruption source. When PXFUN =1, if PXSELX = 0, an altern function 0 is assigned to it, if PXSELX =1, an altern function 1 is assigned to it.

3. Define GPIO address; writting 1 in PXDIRS (output) or in PXDIRC (input).

In order to define an output pin state, processor has two registers, the first one is for keeping a high logic value (PXDATS) and the second one for keeping a low logic value (PXDATC).

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