Analizador de Redes AC

Fs = 958;                    % Sampling frequency
T = 1/Fs;                     % Sample time
L = 16;                     % Length of signal
t = (0:L-1)*T;                % Time vector
% Sum of a 50 Hz sinusoid and a 120 Hz sinusoid
x = sin(2*pi*60*t)*1.75+0.5*sin(2*pi*120*t)+3*sin(2*pi*480*t); 
%y = x + 2*randn(size(t));     % Sinusoids plus noise
stem(t(1:16),x(1:16))
NFFT = 2^nextpow2(L); % Next power of 2 from length of y
Y = fft(x,NFFT)/L;
f = Fs/2*linspace(0,1,NFFT/2+1);

% Plot single-sided amplitude spectrum.
stem(f,2*abs(Y(1:NFFT/2+1)))
ifndef __PLASMA_H__
define __PLASMA_H__

/*********** Hardware addesses ***********/
define RAM_INTERNAL_BASE 0x00000000 //8KB
define RAM_EXTERNAL_BASE 0x10000000 //1MB
define RAM_EXTERNAL_SIZE 0x00100000
define UART_BASE         0x20000000
define UART_WRITE        0x20000000
define UART_READ         0x20000000
define UART_STATUS       0x20000010
define IRQ_MASK          0x20000010
define IRQ_STATUS        0x20000020
define cs_lcd            0x20000030
define cs_fft	         0x20000040
define GPIOA_IN          0x20000050
define COUNTER_REG       0x20000060
define ETHERNET_REG      0x20000070
define FLASH_BASE        0x30000000

/*********** GPIO out bits ***************/
define ETHERNET_MDIO     0x00200000
define ETHERNET_MDIO_WE  0x00400000
define ETHERENT_MDC      0x00800000
define ETHERNET_ENABLE   0x01000000

/*********** Interrupt bits **************/
define IRQ_UART_READ_AVAILABLE  0x01
define IRQ_UART_WRITE_AVAILABLE 0x02
define IRQ_COUNTER18_NOT        0x04
define IRQ_COUNTER18            0x08
define IRQ_ETHERNET_RECEIVE     0x10
define IRQ_ETHERNET_TRANSMIT    0x20
define IRQ_GPIO31_NOT           0x40
define IRQ_GPIO31               0x80

/*********** Ethernet buffers ************/
define ETHERNET_RECEIVE  0x13ff0000
define ETHERNET_TRANSMIT 0x13fe0000

endif //__PLASMA_H__
case(state)
			0:	begin
				if(cs & rw)
					begin
					state<=1;
					spi_rst<=0;
					end
				else
					begin
					ADC_CS<=1;
					spi_rst<=0;
					SPI_en<=0;
					state<=0;					
					end			  	
				end
			1:	begin
				if(n_muestra<1658)
					begin
					ADC_CS<=0;
					spi_rst<=0;
					SPI_en<=1;
					state<=2;
					end
				else
					begin
					ADC_CS<=1;
					spi_rst<=1;
					SPI_en<=0;
					state<=0;
					end
				end
			2:	begin
				SPI_en<=0;
				if(ADC_EOC & (tick_count>22))
					begin
					ADC_CS<=1;
					end
				if(!busy)
					begin
					state<=1;
					end
				end
case (state_spi)
		0:	begin 
				if(SPI_en)
				begin
				clkdiv_en<=1;
				state_spi<=1;
				busy<=1; 
				TX_en_reg<=1;
				end 
			end
		1:	begin
				TX_en_reg<=0;
				if(tick)
					tick_count <= tick_count+1;
				else
				begin
					if(tick_count>55)
					begin
					state_spi<=0;
					tick_count<=0;
					clkdiv_en<=0;
					busy<=0;
						if(n_muestra<1659)
							begin
							if(cont<102)
								cont<=cont+1;
								else
								cont<=0;	
							n_muestra<=n_muestra+1;
							if(cont==101)
							fft_index<=fft_index+1;
							end
						else
							begin
							n_muestra<=0;
							fft_index<=0;
							cont<=0;
							end
					end
				end	
			end
		endcase
Transmisor TX (Envia la configuracion del ADC)
	always@(posedge clk)
	if(reset)
	begin
	in_buffer<=0;
	ADC_SDIN_buffer<=0;
	end
	else
	begin
		if(TX_en_reg && (n_muestra<1))
		begin
		in_buffer<=4'h9;
		if((!posedge_SCLK) & tick)
			begin
			ADC_SDIN_buffer <= in_buffer[3];
			in_buffer<=in_buffer<<1;
			end
		end
		else
		begin
		if(TX_en_reg)
		in_buffer<=4'h1;
			if((!posedge_SCLK) & tick)
			begin
			ADC_SDIN_buffer <= in_buffer[3];
			in_buffer<=in_buffer<<1;
			end
		end
	end	

	assign	ADC_SDIN = ADC_SDIN_buffer;
//Receptor RX_ADC (Recibe los datos del ADC)
	always@(posedge clk)
	begin
	if(cont==50)
	begin
	data_av<=1;
		if((!posedge_SCLK & tick) & (tick_count<21))
		begin
		out_buffer<=(out_buffer<<1);
		out_buffer[0]<=ADC_SDOUT;
		end
	end
	else
	data_av<=0;
	end

	assign data_out = out_buffer;

if(ADC_data_av & !ADC_busy & !core_busy)
						case(data_index)
							0: in_data0<=in_data;
							1: in_data1<=in_data;
							2: in_data2<=in_data;
							3: in_data3<=in_data;
							4: in_data4<=in_data;
							5: in_data5<=in_data;
							6: in_data6<=in_data;
							7: in_data7<=in_data;
							8: in_data8<=in_data;
							9: in_data9<=in_data;
							10: in_data10<=in_data;
							11: in_data11<=in_data;
							12: in_data12<=in_data;
							13: in_data13<=in_data;
							14: in_data14<=in_data;
							15: 
								begin 
								in_data15<=in_data;
								done_reg<=1;
								state<=0; 
								end
							endcase
		case(state2)
			0:	begin
				fwd_inv<=0;
				fwd_inv_we<=0;
				if(done_reg)
				begin
				state2<=1;
				start_fft<=1;
				end
				end
			1:	begin	
					start_fft<=0;
					if(rfd)
					begin
						case(rx_index)
							0: out <= {1'b0,in_data0};
							1: out <= {1'b0,in_data1};
							2: out <= {1'b0,in_data2};
							3: out <= {1'b0,in_data3};
							4: out <= {1'b0,in_data4};
							5: out <= {1'b0,in_data5};
							6: out <= {1'b0,in_data6};
							7: out <= {1'b0,in_data7};
							8: out <= {1'b0,in_data8};
							9: out <= {1'b0,in_data9};
							10: out <= {1'b0,in_data10};
							11: out <= {1'b0,in_data11};
							12: out <= {1'b0,in_data12};
							13: out <= {1'b0,in_data13};
							14: out <= {1'b0,in_data14};
							15: 
								begin 
								out <= {1'b0,in_data15};
								if(abs_done==0)
									begin
									state2 <= 0;
									end
								flag_rx<=1;
								end
							endcase
					end
				end
		endcase
parameter raiz1=	 1'b0;//1
parameter raiz2=	 1'b1;//2	
parameter raiz3=	 3'b100;//4
parameter raiz4=	 5'b10000;//8
parameter raiz5=	 7'b1000000;//16
parameter raiz6=	 9'b100000000;//32
parameter raiz7=	11'b10000000000;//64
parameter raiz8=	13'b1000000000000;//128
parameter raiz9=	15'b100000000000000;//256
parameter raiz10=	17'b10000000000000000;//512
parameter raiz11=	19'b1000000000000000000;//1024
parameter raiz12=	21'b100000000000000000000;//2048
parameter raiz13=	23'b10000000000000000000000;//4096

reg [12:0]
		out_data_abs0,
		out_data_abs1,
		out_data_abs2,
		out_data_abs3,
		out_data_abs4,
		out_data_abs5,
		out_data_abs6,
		out_data_abs7;

//reg[22:0] abs2;
reg[12:0] /*temp1=0,*/temp2;
reg[4:0] state=0,state2=0,state3=0;
reg flag_save=0,abs_flag=0;
reg[15:0] in_real_reg,in_imag_reg;

always@(posedge clk)
begin
	if(reset)
	begin
	FFT_CE<=1;
	temp2<=0;
	temp1<=0;
	state<=0;
	enable_div<=0;
	flag_save<=0;
	unload<=0;
	abs2<=0;
	in_real_reg<=0;
	in_imag_reg<=0;
	end
	else
	begin
		case(state)
		0:
			begin
				if(done_in)
				begin
				state<=1;
				unload<=1;
				end
			end
		1:
			begin
			unload<=0;
				if(data_valid)
				begin
				state<=2;
				end
			end	
		2:
			begin
				FFT_CE<=0;
				flag_save<=0;
				state<=3;
				if(in_real[15]==1)
					in_real_reg<=~in_real+1;
					else
					in_real_reg<=in_real;
				if(in_imag[15]==1)
					in_imag_reg<=~in_imag+1;
					else
					in_imag_reg<=in_imag;
			end	
		3:
			begin
			abs2<=(in_real_reg[13:2]*in_real_reg[13:2])+(in_imag_reg[13:2]*in_imag_reg[13:2]);
			state<=4;
			end
		4:
			begin
				if(abs2 > raiz13)
					begin
					temp1<=4096;
					end
				if(raiz12 < abs2 <= raiz13)
					begin
					temp1<=2048;
					end
				if(raiz11 < abs2 <= raiz12)
					begin
					temp1<=1024;
					end
				if(raiz10 < abs2 <= raiz11)
					begin
					temp1<=512;
					end
				if(raiz9 < abs2 <= raiz10)
					begin
					temp1<=256;
					end
				if(raiz8 < abs2 <= raiz9)
					begin
					temp1<=128;
					end
				if(raiz7 < abs2 <= raiz8)
					begin
					temp1<=64;
					end
				if(raiz6 < abs2 <= raiz7)
					begin
					temp1<=32;
					end
				if(raiz5 < abs2 <= raiz6)
					begin
					temp1<=16;
					end
				if(raiz4 < abs2 <= raiz5)
					begin
					temp1<=8;
					end
				if(raiz3 < abs2 <= raiz4)
					begin
					temp1<=4;
					end
				if(raiz2 < abs2 <= raiz3)
					begin
					temp1<=2;
				end
				if(/*raiz1 <*/abs2 <= raiz2)
					begin
					temp1<=1;
					end
				state<=5;	
			end
			5:
				begin
					enable_div<=1;
					if(done_div)
						begin
						state<=6;
						enable_div<=0;
						end
				end
			6:
				begin
					temp2<=(div+temp1)/2;
					state<=7;
					res_div<=1;
				end
			7:
				begin
					res_div<=0;
					if(temp2 == temp1)
						begin
							if(in_index < 10)
								begin
								flag_save<=1;
								FFT_CE<=1;
								state<=2;
								end
							else
								begin
								state<=0;
								FFT_CE<=1;
								end
						end
					else
						begin
						temp1<=temp2;
						state<=5;
						end
				end
		endcase	
	end
end

always@(posedge clk)
begin
	if(reset)
	begin
		out_data_abs0<=0;
		out_data_abs1<=0;
		out_data_abs2<=0;
		out_data_abs3<=0;
		out_data_abs4<=0;
		out_data_abs5<=0;
		out_data_abs6<=0;
		out_data_abs7<=0;
		state2<=0;
		abs_flag<=0;
	end
	else
	begin
		case(state2)
		0:
			begin
			abs_flag<=0;
			if(done_in)
			state2<=1;
			end
		1:
			begin
			if(flag_save)
				begin
					case(in_index-2)
					0: out_data_abs0 <= temp2;
					1: out_data_abs1 <= temp2;
					2: out_data_abs2 <= temp2;
					3: out_data_abs3 <= temp2;
					4: out_data_abs4 <= temp2;
					5: out_data_abs5 <= temp2;
					6: out_data_abs6 <= temp2;
					7: 	
						begin 
						out_data_abs7 <= temp2;
						state2 <= 0;
						abs_flag<=1;
						end
					endcase	
				end
			end
		endcase	
	end
end
  case(state3)
		0:
			begin
				if(abs_flag)
				begin
				state3<=1;
				abs_done<=1;
				end
			end
		1:
			begin
			if(enable & rd)
				begin
				case(data_index)
				0: out_abs <= out_data_abs0;
				1: out_abs <= out_data_abs1;
				2: out_abs <= out_data_abs2;
				3: out_abs <= out_data_abs3;
				4: out_abs <= out_data_abs4;
				5: out_abs <= out_data_abs5;
				6: out_abs <= out_data_abs6;
				7: 	
						begin 
						out_abs <= out_data_abs7;
						state3 <= 0;
						abs_done<=0;
						end
				endcase	
				end
			end
		endcase	
	end
#include "plasma.h"
#define MemoryRead(A) (*(volatile unsigned long*)(A))
#define MemoryWrite(A,V) *(volatile unsigned long*)(A)=(V)

int main(void)
{
  short i=0;
  unsigned int done;
  MemoryRead(cs_lcd);
  while(1)
  {
  MemoryWrite(cs_fft,0x10);
  //done=(MemoryRead(cs_fft));  
  while(((MemoryRead(cs_fft)) & 0x2000) && 0x2000)  
  {
  for(i=0;i<=7;i++) 
   {
    MemoryWrite(cs_fft,0x20+i); 
    MemoryWrite(cs_lcd, (0x20000 | (1<<17)| /*(0x3E8+(0x3E8*i)*/((MemoryRead(cs_fft) & 0x1FFF))<<4|i));
    }
    i=0; 
   }
  }
  return 0;
}

Semana	Fecha	Actividad
S1	3-8 de ago	Definición del proyecto
S2	10-15 de ago	Investigación
S3	17-22 de ago	Establecimiento de las especificaciones
S4	25-29 de ago	Diseño del circuito de adquisición
S5	31 ago-5 sept	Diseño de la PCB
S6	7-12 de sept	Diseño del algoritmo del FFT
S7	14-19de sept	Fabricación de la PCB del circuito de adquisición
S8	28 sept - 3 de oct	Pruebas y ajustes de PCB, programación hardware y software
S9	5-10 de oct	Programación módulo VGA
S10	12-17 de oct	Programación módulo VGA
S11	19-24 de oct	Programación y pruebas modulo VGA
S12	26-31 de oct	Programación FFT
S13	2-7 de nov	Pruebas del algoritmo FFT
S14	9-14 de nov	Integración del sistema completo
S15	16-21 de nov	Pruebas y ajustes
S16	23-28 de nov	Entrega proyecto final

Costos relacionados al proyecto
Elemento	Descripción	Costo total una unidad	Costo total 100 und
Componentes	Resistencias, condensadores, circuitos integrados, conectores	$72000	$6500000
Circuito impreso	Doble cara, silkscreen	$120000	$2000000
Sie Board	qi-hardware project	$200000	$19000000
Diseño			$8000000
Impuestos	iva, fletes	$50000	$5500000
Total		$442000	$41000000

Analizador de Redes AC

Contents

[edit] Introducción

[edit] Armónicos:

[edit] Efectos de los armónicos en una red AC

[edit] Transformada Rapida de Fourier (FFT)

[edit] Diseño del Circuito

[edit] Sección Análoga

[edit] Sección digital

[edit] Diseño de los módulos en la FPGA

[edit] Mapa de Memoria

[edit] Periferico de manejo del display LCD:

[edit] Configuración del LCD

[edit] Modulo de control LCD:

[edit] Periferico FFT

[edit] Modulo ADC

[edit] Modulo RX

[edit] Core FFT

[edit] Modulo Absolute

[edit] Tareas Software

[edit] Plano de la PCB

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