AVT2 RC2 Reference Board
- 336 MHz XBurst Jz4720 MIPScompatible CPU
- display: 8bit RGB / ITU 656/601 data format input of TFT display.
- dimension (mm): 94.5 x 65
- DRAM: 64MB Synchronous DRAM
- headphone jack (3.5 mm)
- SDHC microSD
- support 850mAh charge limited 4.2V Liion battery
- 2GB NAND flash memory
- miniUSB: USB 2.0 HighSpeed Device
- microAB USB: USB 1.1 Host
- serial console
- speaker and microphone
- 58 Keys
 4 LAYERS
 DESCRIPTIONS of BLOCK
This board has finally 64MB SDRAM with one chip U8 Micron MT48LC32M16A2P75.
 NAND FLASH
This board has SAMSUNG 2GB U9 K9GAG08U0MPCB0.
 USB INTERFACE
There has one USB 1.1 host port with microAB receptacle connector(J4), one USB 2.0 device port on main board (J2).
 AUDIO SYSTEM
JZ4720 provides internal CODEC is an I2S/AC97 audio CODEC with 18 bits DAC and 16 bits ADC. The audio system of this design makes use of the internal CODEC to implement the input and output of audio. It consists of MICin with two solder pads MIC+1 and MIC-1, headphone jack J3, an amplifier U10 GPY0030B for external speaker connecting to the solder pad SP+1 and SP1. When plug a headphone in J3, the amplifier will be off. The audio system provides record with gain control; stereo headphone output with bass/treble boost, and output volume control by software.
 KEYBOARD INTERFACE
There are 58 keys reserved by software control. An another ON/OFF key S9 connected to pin 124 WAKEUP_/PD29 of jz4720. A reset key S1 connected to pin 123 PPRST_ of jz4720. When this pin receives Low, the cpu will start a reset procedure.
 MICROSD CARD SOCKET
J1 is the MICROSD card socket for extension memory.
 LCD INTERFACE
CON2 can let you connected with 24pins of FPC to support 8bit RGB / ITU 656/601 data format input of TFT display.
 CHARGING STATUS LED
LED D3 indicates the charge status that light when charging.
 BOOT SELECT SWITCH
SW1 can be switched to either USB BOOT mode or NAND FLASH BOOT mode.
 SERIAL CONSOLE
CON3 is a serial console with 3 terminals in RXD/TXD/GND fuctionality which can communicate with jz4720.
 JTAG TEST POINTs
There are 5 test points TP1~5 reserved for JTAG interface.
 UART PORT
There is another uart port reserved which shares pins with JTAG interface.
 TOUCH SCREEN INTERFACE
XP/XN, YP/YN reserved inputs for touch screen connection option.
 PROJECT SITE
 CHANGE HISTORY
1. changed U12 Linear LTC3529EDCB to Kingbor KB3436 for cost down
2. changed BD4 into Sunlord ferrite bead PZ1608D221TF and BN1/BN2 changed into Sunlord ferrite bead array ARZ32164601 to pass FCC test.
3. used ST USBDF01W5 for EMI Filter and line termination for USB host downstream ports functionality
4. added CON4P1 footprint available on battery cave for touch screen connection
5. moved SW1 boot slide switch to the left front side and changed to a smaller one
6. added 0.1uF/16V/C0402 between U6 pin1 and pin2 for ESD elimination
7. added R60 100K/5%/R0603 pull high resistor for solving no action during serial connection
 GPIO DEFINITION SHEET
 PCB & GERBER/DRILL FILES
This project is moving on. If you want to see the pcb and gerber files by free Kicad tool, you can check following url ink to see current newest status. http://projects.qi-hardware.com/index.php/p/board-qi-avt2/
 LAYOUT NOTES
- Layout notes avt2 RC2 20091116
- Layout notes avt2 RC2 20091207
- Layout notes avt2 RC2 20091230
- Layout notes avt2 RC2 20100122
- Layout notes avt2 RC2 20100126
- Layout notes avt2 RC2 20100202
 KNOWN ISSUES
Category:Reference Design Board