AVT2 RC1 Reference Board
- 336 MHz XBurst Jz4720 MIPScompatible CPU
- display: 8bit RGB / ITU 656/601 data format input of TFT display.
- dimension (mm): 94.5 x 65
- DRAM: 64MB Synchronous DRAM
- headphone jack (3.5 mm)
- SDHC microSD
- support 850mAh charge limited 4.2V Liion battery
- 2GB NAND flash memory
- miniUSB: USB 2.0 HighSpeed Device
- microAB USB: USB 1.1 Host
- serial console
- speaker and microphone
- 58 Keys
 DESCRIPTIONS of BLOCK
This board has finally 64MB SDRAM with one chip U8 Micron MT48LC32M16A2P75.
 NAND FLASH
This board has SAMSUNG 2GB U9 K9GAG08U0MPCB0.
 USB INTERFACE
There has one USB 1.1 host port with microAB receptacle connector(J4), one USB 2.0 device port on main board (J2).
 AUDIO SYSTEM
JZ4720 provides internal CODEC is an I2S/AC97 audio CODEC with 18 bits DAC and 16 bits ADC. The audio system of this design makes use of the internal CODEC to implement the input and output of audio. It consists of MICin with two solder pastes MIC+1 and MIC-1, headphone jack J3, an amplifier U10 GPY0030B for external speaker connecting to the solder paste SP+1 and SP1. When plug a headphone in J3, the amplifier will be off. The audio system provides record with gain control; stereo headphone output with bass/treble boost, and output volume control by software.
 KEYBOARD INTERFACE
There are 58 keys reserved by software control. An another ON/OFF key S9 connected to pin 124 WAKEUP_/PD29 of jz4720. A reset key S1 connected to pin 123 PPRST_ of jz4720. When this pin receives Low, the cpu will start a reset procedure.
 MICROSD CARD SOCKET
J1 is the MICROSD card socket for extension memory.
 LCD INTERFACE
CON2 can let you connected with 24pins of FPC to support 8bit RGB / ITU 656/601 data format input of TFT display.
 CHARGING STATUS LED
LED D3 indicates the charge status that light when charging.
 BOOT SELECT SWITCH
SW1 can be switched to either USB BOOT mode or NAND FLASH BOOT mode.
 SERIAL CONSOLE
CON3 is a serial console with 3 terminals in RXD/TXD/GND fuctionality which can communicate with jz4720.
 JTAG TEST POINTs
There are 5 test points TP1~5 reserved for JTAG interface.
 UART PORT
There is another uart port reserved which shares pins with JTAG interface.
 TOUCH SCREEN INTERFACE
XP/XN, YP/YN (TP81/TP84, TP82/TP83) test points reserved inputs for touch screen.
 GPIO DEFINITION SHEET
The schematic can be downloaded qi_avt2_v1.0.pdf. All the data sheets of the related parts on this board you can found here. If wants to understand how this open left hardware board working, you can also check our Hardware basics for some basis of hardware involved in NanoNote. If you are interested in waveforms of schematics inside. You can check avt2 waveform page for your help. Be aware of each waveform's duration measured. Their duration which some of them by hardware itself not software control to cause it. Some of them are depended by your software porting. Just see every description of each, then you can check it out. Since avt2 is very likely to Ben NanoNote excepts USB host, you can also see Ben NanoNote's waveform page.
 PCB & GERBER FILES
 LAYOUT NOTES
 KNOWN ISSUES
1. Charge function of U5 SE9016 fail due to wrong pcb footprint layout on U5 pin PROG and VCC reversely. After rework, it works well.
2. USB host functionality failure by wrong design on choosing parts. Instead of USBDF01W5 for EMI Filter and line termination for USB downstream ports. After rework, it works well.
3. BD4 needed to be changed into Sunlord ferrite bead PZ1608D221TF and BN1/BN2 needed to be changed into Sunlord ferrite bead array ARZ32164601 to pass FCC test.
4. Not easily plugin the CON2 fpc connector, after using TONYO's BL11424RLTAND. It connects well.
5. J1 microSD socket is out of placements a little.
6. Keys are out of placement met with mechanical metal domn, but still works well.
7. Y1 32.768KHz Xtal is not at right spec, after changing to YOKETANT P1AT26070327681220AD. It works well.
Category:Reference Design Board