ASIC production notes
From Qi-Hardware
XiAn University of Technology main entrance 34.25340,108.98819 EE building 34.25490,108.99062 works on new beitou only gps receiver chip hasnt heard about highvision Fuji in Shanghai is offering IC design services classmate of his working there verilog to gdsII to foundry maybe infrared ic is the simplest most work is digital ic, some analog uwb work but cancelled send verilog 1 month later can return gdsii 5 people needed, 20% design, 80% verification 80-100k RMB price for more complex chip almost the same, suggests foundry needs 60-90 days 50 samples cost 80-100k rmb mostly for film can be reused for producing 2-3k chips suggests to not go to full wafer film right away then 200-300k rmb for whole wafer film suggested wuxi company one wafer 200-300k rmb mpw share 2000nm process 350nm up to 5k gate use 1000nm 10k-50k gate use 350nm above 50k gate use 180nm for 500nm process costs 10-20k rmb for 50 samples in mpw for 350nm more service is included guess for 4720 is 500k to 1m gates 1 6inch wafer costs 1000rmb package into qfp for 100rmb/sample 90% of wafer can be used for a 4x4mm die 700-1000 fit on one 6inch wafer film can be used for several years 500nm mask for 10-20k rmb is slower, 3 months need to design all gates, then can take to other foundries as well, no copyright problem foundry only provides layout design rules, then we need to design all gates in this case we can publish the gate cells the layout of every gate can be copyrighted we need to construct the basic gate cells ourselves 4 independent small foundries in china hua hung, he jian run verilog in mentorgraphics modelsim, mentorgraphics cadence ncverilog design compiler synopsis encounter autorouter/autolayout (cadence) creates gdsii file verification: pt/synopsis post simulator modelsim mentorgraphics calibre for optical verification basic gate cell design: cadence visual layout, will create library for encounter Q: How big is the team? A: 30-40 profs/teachers/workers, 20-30 grad students How safe is it to buy used chips, like FPGAs or NAND. I see them a lot in Shenzhen. How can a used chip be tested? use jtag to test used chips like fpgas. he likes to use 2nd hand chips test cost for die or bga are high 2nd hand may only cost 30% of new one must use jtag to test every pin, uses perl script static electricity will only damage i/o pins dc compiles into verilog gatelist design for test - dft
- meeting with Chitlesh Goorah from Free Electronic Lab, January 8, 2011
tcl scripting in synopsis, cadence, mentorgraphics is industry standard, free tools should support it too free tools don't support standard industry file formats well, for example (all text based): liberty - timing, see http://www.opensourceliberty.org/ lef (supported by magic) - metallization representation in silicon (cadence) ict - interconnect parasitics (cadence) spef - parasitics captable - capacitance, resistance per wire length