Milkymist One RC2 Layout History

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The histories here are the whole relationships between placements, layout criteria and relevant routings. All the info here you can take a look or reference. We're trying to record all the concerns of how routing, how this moving on and what did we do. No matter what we might encounter a wrong direction potentially or even correct direction. So we encourage people who possesses solid experiences in this layout industry to have fun and give us feedbacks which could nourish this copyleft hardware as an amusement park here.

Contents

20101102

  • Put more one via on +5V and ground trace loop. Compared to preceding version, check 20101028.

  • Add circular positive and negative mark. Compared to preceding version, check 20101028.

  • Move C240 close to C165. Compared to preceding version, check 20101028.

This version is based on http://lists.milkymist.org/pipermail/devel-milkymist.org/2010-October/000994.html And the following items have been changed: 

 1, U10 pad1/3 dimension is 66.929 x 51.181 mil.
 2, Fixed & Updated MilkymistOne.SchLib, MilkymistOne.PcbLib, MilkymistOne.LibPkg

This version has three classes of Rule Violations which totally over more than 500 items when you execute DRC:

  • 1), 388 items of [Matched Net Lengths(Tolerance=200mil) (Amplitude =200mil) (Gap=20mil) (Style=90-Degree) (InNetClass('All Nets'))], ruled by 'Default' PADS rule_7 of Matched Net Lengths of High Speed. This is used on designing High Speed pcb with specified Tolerance, Amplitude, Gap and Style elements. Xilinx uses
  • 2), 83 items of [Parallel Segment Constraint (Gap=200mil ) (Limit=1000mil) (All),(All)], ruled by 'Default' PADS rule_2 and 'Default' PADS rule_3 of Parallel Segment of High Speed. PADS rule_2 is for same layer checking for a parallel gap of 200mil, the parallel limit length is 1000mil. PADS rule_3 is for adjacent layer checking which is same as rule_2. Both RC2 don't need them. RC1 is disable.
  • 3), 29 items of [Hole Size Constraint (Min=1mil) (Max=100mil) (All)], ruled by HoleSize of Hole Size of Manufacturing. This Hole Size is ruled from minimum 1 mil to 100mil. In a general, actually one pcb uses several 'Hole Size' of vias. RC1 is diable, RC2 needs disable this.

20101028

  • Slight moved back 1V2 decoupling capacitors forwarding to centeral pins of FPGA but not all because of via placemented under FPGA are all through holes not blind and buried vias which can place capacitors on bottom as closer as to center. See discussion. Or compared to preceding version, check 20101018 1V2 Decoupling Capacitors.

  • To Be Done: The C240 1210 100uF decoupling capacitor should be close to C165 as possible.

  • RC2 used resistors to set hardware version. R176/177/178/179 are placed in a row on Top side. The RC2 board should be encoded as 0001 (ie place only 1 resistor) to distinguish it from RC1 which does not have any resistor. Use 1K resistors for pull-ups.

  • Indicate "+/- 5%" and pinout (positive in the middle) near J11 on silkscreen. To prevent from a novice who uses wrong polarity of DC adapter +5V inlet, we should add an icon to indicate correct polarity like SIE DC Jack's icon.

  • Make a larger soldered area under the pads of U10. To improve this, used several GND via instead of "cross" pad on GND plate to let heat conducted on both top / bottom GND plate to get good dissipation. Compared to preceding version, check RC1 U10's footprint

  • Make a larger soldered area under the pads of U13. Changed U13's cross to have a bigger GND plate on Top side but no changes on Bottom side. Compared to preceding version, check RC1 U13's footprint

  • Retain C240, C242, C243, C244, C245 decoupling capacitors, compared to preceding 20101018 modification.

  • Retain C248, C250, C251, C252 decoupling capacitors but C247 will be deleted next modification, compared to preceding 20101018 modification.

  • R166, R167, 15K for U16. R168, DNP, 1.5K, FULL SPEED setting. R169, DNP, 1.5K, LOW SPEED setting. R170, R171, 15K for U17. R172, DNP, 1.5K, FULL SPEED. R173, DNP, 1.5K, LOW SPEED. Compared to preceding version, check 20101018.

  • Changed MK1 footprint to meet part. Compared to preceding version, check RC1 MK1's foortprint

  • Moved clearance to near J12. Compared to preceding version, check 20101018. Also change the inner diameter of 4 mechanical through holes(J12/J13/J14/J15) on board from 3 to 3.2mm.

  • To Be Done: put more one via on +5V and ground trace loop. Placement via as marks in pink color circles.

20101018

  • Connect P[15:8] instead of P[7:0] on the video decoder chip U21.

  • Changed to new part 6N138S photocoupler. Changed U6 to 6N138S footprint.

  • Added TPs on signals path between USB chips and fpga, and resistors placeholders.

  • Enhance DDRRAM power noise immunity:

  • Fg. 1

  • Fg. 2

  • Strengthen independantly power or ground driven pin of FPGA:

  • Good power or ground pins with one via each.

  • Decoupling Capacitors surrouding centeral pins of FPGA. This is still not good enough, can be improved. See discussion.

  • Added routing for parts of 4.3V Power Supply

  • Added routing for 4.3V Power Supply. To be given a clearance between GND and J12.

  • Given several vias to connect decoupling capacitors whenever possible, especially the big ones. See below.

  • Fg. 1:

  • Fg. 2:

  • Fg. 3:

  • Fg. 4:

  • Fg. 5:

  • Fg. 6:

  • Fg. 7:

20100929

  • Strengthen independantly power or ground driven pin of FPGA:

  • Fg. 1: Another good power or ground pins with vias example which stacked up to a 16-layers pcb.

  • Fg. 2: M1 RC1, Good Via routing to power or ground pin of FPGA.

  • Fg. 3: M1 RC1, Bad power or ground pins of FPGA share from one via.

  • Fg. 4: M1 RC1, Bad power or ground pins of FPGA share from one via of decoupling capacitors. Each via must serve its fpga pin or capacitor only. 

 Corrective Action: In Fg. 3 that shows most of 1V2 or ground pins of FPGA share with one via source. 
 This must be corrected with using at least 1 via for each power or ground pin of FPGA.

In Fg. 1 shows that each pin of FPGA connects to each only one via. This approach is resorted to a more layers like this is a 16-layers pcb. The L16_BOTTOM layer is in dark gray color, L1_TOP layer is in light gray color, L15_PWR is power layer, L2_GND(not shown) and SILK_BOT is in red color. To let a 6-layers stacking with all power and ground pins connected to each independant via sometimes is not possible but wherever possible.

  • Enhance DDRRAM power noise immunity:

  • Fg. 1: M1 RC1 U14 DDRRAM decoupling capacitors placement/routing which do not completely enhance noise immunity.

  • Fg. 2: M1 RC2 U14 DDRRAM : Plan to add more decoupling capacitors placement/routing which is marked in cyan color of squares to enhance noise immunity.

  • Fg. 3: M1 RC1 U15 DDRRAM decoupling capacitors placement/routing which do not completely enhance noise immunity.

  • Fg. 4: M1 RC2 U15 DDRRAM : Plan to add more decoupling capacitors placement/routing which is marked in cyan color of squares to enhance noise immunity. 

 Corrective Actions: In Fg. 1 that needs to add 100uF at nearby pins 1/18/33 each for VDD, and add 100nF
 at nearby pins 3/9/15/55/61 each for VDDQ. Same methods at U15 in Fg. 3. Also add several vias to 
 connect decoupling capacitors whenever possible, especially the big ones (100uF). With adding more
 capacitors corrected in Fg. 2 and 4. Big squares are 100uF, the small squares are 100nF.

From Micron TN-46-14 p.14 subtitle of Decoupling, it said that VDD is digital power for the device core and VDDQ is power for the DQ and I/O signals. So recommends at least four low (2nH) effective series inductance (ESL) capacitors per DDR component to decouple VDD/VDDQ from VSS/VSSQ. Values from 0.01–0.22μF balance well in bypassing higher-frequency (0.01μF) and lower-frequency (0.22μF) noise. If a frequency spectrum characterizing power-supply noise can be generated, choosing capacitors to optimize decoupling at certain frequencies (where noise peaks)is preferred. Associated technical note called "DECOUPLING CAPACITOR CALCULATION FOR A DDR MEMORY CHANNEL" goes deep into technical parameters determined with via. Although it recommends to use a low ESL capacitor which always have higher price than general purpose MLCC (Fg. RC1 C162/100nF/X5R). So just adding and keeping using more capacitors used in RC1 seems a good solution.

  • Given several vias to connect decoupling capacitors whenever possible, especially the big ones.

The following pictures are all being needed to add more vias at the pads of decoupling capacitors, especially the 100uF(1210 package). Although these bad routing do not alter the functionality of the RC1 board, we still can give improvement on them.

  • Fg. 1:

  • Fg. 2:

  • Fg. 3:

  • Fg. 4:

  • Fg. 5:

  • Fg. 6:

  • Fg. 7:

  • Planed a placement area for parts of 4.3V Power Supply

  • Decided placement area. Make same clearance between J12 and pwer area.

  • Improvement solderibility during SMD reflowing

See also RC1 Layout History

Milkymist One RC1 Layout History

Link

Reference

  1. ↑ TOMBSTONING OF 0402 AND 0201 COMPONENTS: "A STUDY EXAMINING THE EFFECTS OF VARIOUS PROCESS AND DESIGN PARAMETERS ON ULTRA-SMALL PASSIVE DEVICES"
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