Milkymist One RC2 Layout History

The histories here are the whole relationships between placements, layout criteria and relevant routings. All the info here you can take a look or reference. We're trying to record all the concerns of how routing, how this moving on and what did we do. No matter what we might encounter a wrong direction potentially or even correct direction. So we encourage people who possesses solid experiences in this layout industry to have fun and give us feedbacks which could nourish this copyleft hardware as an amusement park here.

20101013

• Added routing for parts of 4.3V Power Supply

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  Added routing for 4.3V Power Supply.

• Given several vias to connect decoupling capacitors whenever possible, especially the big ones. See below.

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  Fg. 1:

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  Fg. 2:

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  Fg. 3:

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  Fg. 4:

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  Fg. 5:

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  Fg. 6:

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  Fg. 7:

20100929

• Strengthen independantly power or ground driven pin of FPGA:

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  Fg. 1: Another good power or ground pins with vias example which stacked up to a 16-layers pcb.

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  Fg. 2: M1 RC1, Good Via routing to power or ground pin of FPGA.

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  Fg. 3: M1 RC1, Bad power or ground pins of FPGA share from one via.

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  Fg. 4: M1 RC1, Bad power or ground pins of FPGA share from one via of decoupling capacitors. Each via must serve its fpga pin or capacitor only.

 Corrective Action: In Fg. 3 that shows most of 1V2 or ground pins of FPGA share with one via source. 
 This must be corrected with using at least 1 via for each power or ground pin of FPGA.

In Fg. 1 shows that each pin of FPGA connects to each only one via. This approach is resorted to a more layers like this is a 16-layers pcb. The L16_BOTTOM layer is in dark gray color, L1_TOP layer is in light gray color, L15_PWR is power layer, L2_GND(not shown) and SILK_BOT is in red color. To let a 6-layers stacking with all power and ground pins connected to each independant via sometimes is not possible but wherever possible.

• Enhance DDRRAM power noise immunity:

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  Fg. 1: M1 RC1 U14 DDRRAM decoupling capacitors placement/routing which do not completely enhance noise immunity.

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  Fg. 2: M1 RC2 U14 DDRRAM : Plan to add more decoupling capacitors placement/routing which is marked in cyan color of squares to enhance noise immunity.

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  Fg. 3: M1 RC1 U15 DDRRAM decoupling capacitors placement/routing which do not completely enhance noise immunity.

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  Fg. 4: M1 RC2 U15 DDRRAM : Plan to add more decoupling capacitors placement/routing which is marked in cyan color of squares to enhance noise immunity.

 Corrective Actions: In Fg. 1 that needs to add 100uF at nearby pins 1/18/33 each for VDD, and add 100nF
 at nearby pins 3/9/15/55/61 each for VDDQ. Same methods at U15 in Fg. 3. Also add several vias to 
 connect decoupling capacitors whenever possible, especially the big ones (100uF). With adding more
 capacitors corrected in Fg. 2 and 4. Big squares are 100uF, the small squares are 100nF.

From Micron TN-46-14 p.14 subtitle of Decoupling, it said that VDD is digital power for the device core and VDDQ is power for the DQ and I/O signals. So recommends at least four low (2nH) effective series inductance (ESL) capacitors per DDR component to decouple VDD/VDDQ from VSS/VSSQ. Values from 0.01–0.22μF balance well in bypassing higher-frequency (0.01μF) and lower-frequency (0.22μF) noise. If a frequency spectrum characterizing power-supply noise can be generated, choosing capacitors to optimize decoupling at certain frequencies (where noise peaks)is preferred. Associated technical note called "DECOUPLING CAPACITOR CALCULATION FOR A DDR MEMORY CHANNEL" goes deep into technical parameters determined with via. Although it recommends to use a low ESL capacitor which always have higher price than general purpose MLCC (Fg. RC1 C162/100nF/X5R). So just adding and keeping using more capacitors used in RC1 seems a good solution.

• Given several vias to connect decoupling capacitors whenever possible, especially the big ones.

The following pictures are all being needed to add more vias at the pads of decoupling capacitors, especially the 100uF(1210 package). Although these bad routing do not alter the functionality of the RC1 board, we still can give improvement on them.

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  Fg. 1:

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  Fg. 2:

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  Fg. 3:

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  Fg. 4:

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  Fg. 5:

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  Fg. 6:

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  Fg. 7:

• Planed a placement area for parts of 4.3V Power Supply

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  Decided placement area. Make same clearance between J12 and pwer area.

• Improvement solderibility during SMD reflowing

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  Suggested good stencil aperture dimension on 0402 and 0603 package.

Link

• Milkymist One Layout Criteria