Milkymist One Power On Off Sequence

Normal RC2 Power On Off Sequence

• 

  Fig. 1, Booted: A manuscript of illustrating Milkymist One RC2 0x1a board. It is collected from Milkymist One RC2 Collective Waveforms Captured While Power On/Off.

Known un-booted conditions

Fig. 2, With Sch. 1. How "fast" power cycling it is!

When unbooted condition is happened, the LED D2,D3 lights slightly. You probably can boot next power plug-in or never boot at all forever.

• Rarely happens: even power adapter plugs-in.
• Often appears: power on then off, and power on again with tiny duration said like below 100ms.

The schematics of three experiments

• 

  Sch. 1: Original RC2 design schematic.

• 

  Sch. 2: added A4806E3R-30N low voltage detector with 20us delay without diode.

• 

  Sch. 3: added A4809E3R-263DN low voltage detector with 200ms delay and a MSCD104H diode.

Configuration Sequence

Fig. 3, FPGA Cofiguration Sequence

Usefull pin of FPGA Configuration

• PROGRAM_B : It's a dedicated input pin for Active-Low asynchronous full-chip reset. When asserted Low for 500 ns or longer, forces the FPGA to restart its configuration process by clearing configuration memory and resetting the DONE and INIT_B pins after PROGRAM_B returns High.
• During Configuration: Must be High to allow configuration to start.
• After Configuration: Drive PROGRAM_B Low and release to reprogram FPGA. Hold ROGRAM_B to force the FPGA I/O pins into High-Z, allowing direct programming access to SPI flash PROM pins.

• Waveforms on board with Sch. 1
• 

  Fig. 4, Un-booted: MM1 RC2 0x2c board; CH1 = DONE(triggered source), CH2 = PROGRAM_B; triggered at rising edge by switching on -> off -> on an AC 110V from the input of AC(EU) DC adapter WN10B-050; without reset ic, no 82nF besides R60, power cycling : On(D2 lights flash) -> Off -> On(D2 slight lights eventually), Monitor Milkymist logo doesn't show up. 100m sec/div

• Waveforms on board with Sch. 2
• 

  Fig. 5, Un-booted: MM1 RC2 0x2c board; CH1 = DONE(triggered source), CH2 = PROGRAM_B'; triggered at rising edge by switching on -> off -> on an AC 110V from the input of AC(EU) DC adapter WN10B-050; with reset ic 20us delay connected to PROGRAM_B, no 82nF besides R60, power cycling : On(D2 lights flash) -> Off -> On(D2 lights off eventually), Monitor Milkymist logo shows up but doesn't enter Flicknoise control panel screen.100m sec/div

• 

  Fig. 6, Booted: MM1 RC2 0x2c board; CH1 = DONE(triggered source), CH2 = PROGRAM_B'; triggered at rising edge by switching on -> off -> on an AC 110V from the input of AC(EU) DC adapter WN10B-050; with reset ic 20us delay connected to PROGRAM_B, power cycling : On(D2 lights flash) -> Off -> On(D2 lights off eventually), Monitor Milkymist logo shows up and enters Flicknoise control panel screen.250m sec/div

• Waveforms on board with Sch. 3
• 

  Fig. 7, Booted: MM1 RC2 0x2c board; CH1 = DONE(triggered source), CH2 = PROGRAM_B; triggered at rising edge by switching on -> off -> on an AC 110V from the input of AC(EU) DC adapter WN10B-050; with A4809E3R-263DN reset ic 200ms delay & diode connected to PROGRAM_B, power cycling : On(D2 lights flash) -> Off -> On(D2 lights off eventually), Monitor Milkymist logo shows up also enter Flicknoise control panel screen.100m sec/div

Power-On Sequence Precautions for FPGA.

One of the following system design approaches can ensure that the SPI flash is ready to receive commands before the FPGA starts its configuration procedure:

1. Control the sequence of the power supplies such that the SPI flash is certain to be powered and ready
 for asynchronous reads before the FPGA begins its configuration procedure.
2. Hold the FPGA PROGRAM_B pin Low from power-up to delay the start of the FPGA configuration procedure
 and release the PROGRAM_B pin to High after the SPI flash is fully powered and is able to receive 
 commands.
3. Hold the FPGA INIT_B pin Low from power-up to delay the start of the FPGA configuration procedure and 
 release the INIT_B pin to High after the SPI flash becomes ready to receive commands.

Since this statement describes about SPI flash, but its explaination is still usefull to other derivatives. It especially expresses why our boot bug could be also happened on BPI NOR flash.

JS28F256J3F105 NOR FLASH Reset Specifications

It's power supply sequencing is not required if VPEN is connected to VCC or VCCQ. In this Milkymist One's design, the VPEN is thus connected to VCC and VCCQ. It's thus 3V3 net. But Power supply transitions should only occur when RP# is low. This protects the device from accidental programming or erasure during power transitions. Unfortunately the RC2's design doesn't take this consideration. From Normal RC2 Power On Off Sequence, we can see RP# almost goes high which shows it synchronized to VCCQ! But data sheet says at least 300us for VCC power valid to RP# high level. Check following waveform scoped which indeed violates recommendation.

• Waveforms on board with Sch. 1 or Sch. 2
• 

  Fig. 8, CH1 = 3V3, CH2 = U9 RP# pin; No matter what booted or unbooted case, the waveform is badly formed as shown. Even it's already added reset ic 20us on PROGRAM_B pin.

• Waveforms on board with Sch. 2
• 

  Fig. 9, Un-booted: MM1 RC2 0x2c board; CH1 = DONE(triggered source), CH2 = U9 RP#; triggered at rising edge by switching on an AC 110V from the input of AC(EU) DC adapter WN10B-050; with reset ic 20us delay connected to PROGRAM_B, No 82nF, power cycling : On(D2 slight flash) -> Off -> On(D2 lights On eventually), Monitor Milkymist logo shows up but doesn't enter Flicknoise control panel screen.100m sec/div

• 

  Fig. 10, Booted: MM1 RC2 0x2c board; CH1 = DONE(triggered source), CH2 = U9 RP#; triggered at rising edge by switching off an AC 110V from the input of AC(EU) DC adapter WN10B-050; with reset ic 20us delay connected to PROGRAM_B, no 82nF besides R60, power cycling : On(D2 lights flash) -> Off -> On(D2 lights off eventually), Monitor Milkymist logo shows up and also enters Flicknoise control panel screen.250m sec/div

• Waveforms on board with Sch. 3
• 

  Fig. 11, CH1 = 3V3, CH2 = U9 RP# pin; No matter what booted or unbooted case, the waveform is expectedly formed as shown. Added reset ic 200ms on PROGRAM_B pin and 1 diode on RP#.

• 

  Fig. 12, CH1 = 3V3, CH2 = U9 RP# pin; No matter what booted or unbooted case, the waveform is expectedly formed as shown. Added reset ic 200ms on PROGRAM_B pin and 1 diode on RP#.

• 

  Fig. 13, CH1 = RPOGRAM_B, CH2 = U9 RP# pin; the waveform is expectedly formed as shown. Added reset ic 200ms on PROGRAM_B pin and 1 diode on RP#.

Asserting RP# during a system reset is important with automated program/erase devices because systems typically expect to read from flash memory when coming out of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization may not occur. This is because the flash memory may be providing status information, instead of array data as expected. Connect RP# to the same active low reset signal used for CPU initialization. Also, because the device is disabled when RP# is asserted, it ignores its control inputs during power-up/down. Invalid bus conditions are masked, providing a level of memory protection. See Reset Operation Waveforms in JS28F256J3F105.

1, tVCCPH: Min. 300us, VCC Power valid to RP# de-assertion (high)
2, tPLPH: Min. 100ns, RP# pulse width low

Results

• With Sch. 3:

1. After fast power cycling about 9 or 10 times, got msg log below, with D2 lights well, D3 is OFF.

• Msg logs on board with Sch. 3
• 

  Fig. 14,

2. forgot to capture waveform on this, power off then on; reflashing image again 3. After reflash, power-on then press mid-switch, D2 lights but screen shows nothing (in black) anyway 4. power off and wait for about 1 hr(just for lunch) 5. then power-on again, from now on; m1 easily enters unbooted more even just when power on. So tried to get and screen shows, D2 light well, D3 is OFF:

libHPDMC SDRAM initialization runtime
(c) Copyright 2010 Sebastien Bourdeauducq, released under GNU LGPL version 3.
Version 1.0RC1

Initialization sequence completed.
Autocalibration OK, testing memory...
Memory test failed, entering manual mode.

u: inc. DQ delay  // d: dec. DQ delay
t: test (small)   // T: test (large)
c: calibrate IODELAY2s
r: reset IODELAY2s
p: display pattern
b: boot
019

• Screen shown that board with Sch. 3
• 

  Fig. 15,

6. then board is always unbooted, so waveforms measured as below:

• Waveform shown that board with Sch. 3
• 

  Fig. 16, CH1 = DONE, CH2 = PROGRAM_B; There's no pull high(means FPGA configuration finished). Meawhile the waveform of RP# is syncronized to PROGRAM_B.

7. still under checking why?

Links

Operating Voltages of Milkymist One's Key Parts

Milkymist One RC2 Collective Waveforms Captured While Power On Off

Spartan-6 - Why is INIT_B low after power-on?

Xilinx UG394 Spartan-6 FPGA Power Management User Guide

Configuring Xilinx FPGAs with SPI Serial Flash

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics