Milkymist One Layout Criteria
From Qi-Hardware
Paying more attention on any layout suggestions from datasheet of critical parts is to make good route solutions and get reliability expectedly while layout process. Here is to summarize those information including general rules and strongly recommended reminders. You could face this stage to build your expectative performance like check list which to reach results as same as chip provider suggested.
Contents |
Schematics Symbols Review
- Check for stupid errors like swapped or missing pins.
Footprint Review
- Compare all data (pin numbers, geometries, plated/non-plated holes, ...) in the footprint libraries with the drawings in the datasheets.
FPGA layout
- Layout guidelines (including instructions for the placement of the numerous decoupling capacitors) are documented in UG393, available from Xilinx or the datasheet repository.
FPGA pins assignment
- You can swap pins to make routing easier, but be careful of the special function pins (global clock capable pins, and pins that have a special behaviour during configuration). Most pins going to the Flash are not swappable because the Flash is used to configure the FPGA.
DDR SDRAM layout
- A good document is available from Micron: http://download.micron.com/pdf/technotes/DDR/tn4614.pdf This document also recommends PCB layer stackups that we should use. I would choose the 4 signal layers option with 2 power planes. We'll use series terminations only with very short traces going to the FPGA. Do not spend too much effort on equalizing trace lengths. We have the FPGA's IODELAY elements to compensate for signal propagation delay discrepancies, and, contrary to length-equalizing (and length-increasing) zigzags, they do not cause additional signal integrity issues (ringing, noise, etc.). If you have time and an IBIS simulator, it would be a good idea to run a signal integrity simulation on the final routing. IBIS models for the FPGA's I/O cells can be downloaded from http://www.xilinx.com/support/download/sp6ibis.htm and those for the DRAM: http://download.micron.com/downloads/models/ibis/sdram/ddr/512meg/t37z_ibis.zip
Ethernet Routing
- There are some tips available at: http://pcb1001.blogspot.com/2009/07/ethernet-component-layout-guidelines.html We have integrated magnetics. These rules might be a little overkill, I know of several working Ethernet boards that do not respect them. In case of conflicts (for example, about board stackup), priority should be gived to notorious sources of problems like DDR SDRAM.
ESD Protection
- As you may have noticed, there are several ESD protection cells made of a 1M resistor and a 4.7nF capacitor in parallel. You may want to cut the ground plane and add a little metal polygon under and around the concerned connectors, connected to their shells. Then place that ESD protection cells between the polygon and the ground plane. The Zener diodes near the DMX connectors are not meant to protect against ESD, but against clumsy users connecting microphone cables with 48V phantom power
to the DMX plugs.
