LCD

La siguiente tabla muestra los registros que utiliza el controlador de LCD del JZ4720. [*TRANSLATE PLEASE]

Name register	Type	Initial value	Address	Size
LCDCFG	RW	0x00000000	0x13050000	32
LCDVSYNC	RW	0x00000000	0x13050004	32
LCDHSYNC	RW	0x00000000	0x13050008	32
LCDVAT	RW	0x00000000	0x1305000C	32
LCDDAH	RW	0x00000000	0x13050010	32
LCDDAV	RW	0x00000000	0x13050014	32
LCDPS	RW	0x00000000	0x13050018	32
LCDCLS	RW	0x00000000	0x1305001C	32
LCDSPL	RW	0x00000000	0x13050020	32
LCDREV	RW	0x00000000	0x13050024	32
LCDCTRL	RW	0x00000000	0x13050030	32
LCDSTATE	RW	0x00000000	0x13050034	32
LCDIID	R	0x00000000	0x13050038	32
LCDDA0	RW	0x00000000	0x13050040	32
LCDSA0	R	0x00000000	0x13050044	32
LCDFID0	R	0x00000000	0x13050048	32
LCDCMD0	R	0x00000000	0x1305004C	32
LCDDA1	RW	0x00000000	0x13050050	32
LCDSA1	R	0x00000000	0x13050054	32
LCDFID1	R	0x00000000	0x13050058	32
LCDCMD1	R	0x00000000	0x1305005C	32

kernel source

FILE: arch/mips/include/asm/mach-jz4740/regs.h

LCD controller base registers definition.

...
 #define	LCD_BASE	0xB3050000
 #define	SLCD_BASE	0xB3050000
...
 /*************************************************************************
  * LCD (LCD Controller)
  *************************************************************************/
 #define LCD_CFG	(LCD_BASE + 0x00) /* LCD Configure Register */
 #define LCD_VSYNC	(LCD_BASE + 0x04) /* Vertical Synchronize Register */
 #define LCD_HSYNC	(LCD_BASE + 0x08) /* Horizontal Synchronize Register */
 #define LCD_VAT	(LCD_BASE + 0x0c) /* Virtual Area Setting Register */
 #define LCD_DAH	(LCD_BASE + 0x10) /* Display Area Horizontal Start/End Point */
 #define LCD_DAV	(LCD_BASE + 0x14) /* Display Area Vertical Start/End Point */
 #define LCD_PS	(LCD_BASE + 0x18) /* PS Signal Setting */
 #define LCD_CLS	(LCD_BASE + 0x1c) /* CLS Signal Setting */
 #define LCD_SPL	(LCD_BASE + 0x20) /* SPL Signal Setting */
 #define LCD_REV	(LCD_BASE + 0x24) /* REV Signal Setting */
 #define LCD_CTRL	(LCD_BASE + 0x30) /* LCD Control Register */
 #define LCD_STATE	(LCD_BASE + 0x34) /* LCD Status Register */
 #define LCD_IID	(LCD_BASE + 0x38) /* Interrupt ID Register */
 #define LCD_DA0	(LCD_BASE + 0x40) /* Descriptor Address Register 0 */
 #define LCD_SA0	(LCD_BASE + 0x44) /* Source Address Register 0 */
 #define LCD_FID0	(LCD_BASE + 0x48) /* Frame ID Register 0 */
 #define LCD_CMD0	(LCD_BASE + 0x4c) /* DMA Command Register 0 */
 #define LCD_DA1	(LCD_BASE + 0x50) /* Descriptor Address Register 1 */
 #define LCD_SA1	(LCD_BASE + 0x54) /* Source Address Register 1 */
 #define LCD_FID1	(LCD_BASE + 0x58) /* Frame ID Register 1 */
 #define LCD_CMD1	(LCD_BASE + 0x5c) /* DMA Command Register 1 */
...

LCD configure register definition.

Bit de selección:

...
 /* LCD Configure Register */
 #define LCD_CFG_LCDPIN_BIT	31  /* LCD pins selection */
...

LCD Pin Select bit function description:

LCDPIN Value	Function
0	LCD PIN, select standard LCD
1	SLCD PIN, select smart LCD

...
 #define LCD_CFG_LCDPIN_MASK	(0x1 << LCD_CFG_LCDPIN_BIT)
 #define LCD_CFG_LCDPIN_LCD	(0x0 << LCD_CFG_LCDPIN_BIT)
 #define LCD_CFG_LCDPIN_SLCD	(0x1 << LCD_CFG_LCDPIN_BIT)
...

Los bits del 30:24 son reservados, cuando se intentan leer devulven '0' y no escriben nada.

Definición Bits 23:8 :

...
 #define LCD_CFG_PSM		(1 << 23) /* PS signal mode */
 #define LCD_CFG_CLSM		(1 << 22) /* CLS signal mode */
 #define LCD_CFG_SPLM		(1 << 21) /* SPL signal mode */
 #define LCD_CFG_REVM		(1 << 20) /* REV signal mode */
 #define LCD_CFG_HSYNM		(1 << 19) /* HSYNC signal mode */
 #define LCD_CFG_PCLKM		(1 << 18) /* PCLK signal mode */
 #define LCD_CFG_INVDAT	(1 << 17) /* Inverse output data */
 #define LCD_CFG_SYNDIR_IN	(1 << 16) /* VSYNC&HSYNC direction */
 #define LCD_CFG_PSP		(1 << 15) /* PS pin reset state */
 #define LCD_CFG_CLSP		(1 << 14) /* CLS pin reset state */
 #define LCD_CFG_SPLP		(1 << 13) /* SPL pin reset state */
 #define LCD_CFG_REVP		(1 << 12) /* REV pin reset state */
 #define LCD_CFG_HSP		(1 << 11) /* HSYNC pority:0-active high,1-active low */
 #define LCD_CFG_PCP		(1 << 10) /* PCLK pority:0-rising,1-falling */
 #define LCD_CFG_DEP		(1 << 9)  /* DE pority:0-active high,1-active low */
 #define LCD_CFG_VSP		(1 << 8)  /* VSYNC pority:0-rising,1-falling */
...

...
 #define LCD_CFG_PDW_BIT	4  /* STN pins utilization */
 #define LCD_CFG_PDW_MASK	(0x3 << LCD_DEV_PDW_BIT)
...

...
 #define LCD_CFG_PDW_1		(0 << LCD_CFG_PDW_BIT) /* LCD_D[0] */
 #define LCD_CFG_PDW_2		(1 << LCD_CFG_PDW_BIT) /* LCD_D[0:1] */
 #define LCD_CFG_PDW_4		(2 << LCD_CFG_PDW_BIT) /* LCD_D[0:3]/LCD_D[8:11] */
 #define LCD_CFG_PDW_8		(3 << LCD_CFG_PDW_BIT) /* LCD_D[0:7]/LCD_D[8:15] */
...

...
 #define LCD_CFG_MODE_BIT	0  /* Display Device Mode Select */
 #define LCD_CFG_MODE_MASK	(0x0f << LCD_CFG_MODE_BIT)
...

...
 #define LCD_CFG_MODE_GENERIC_TFT	 (0 << LCD_CFG_MODE_BIT) /* 16,18 bit TFT */
 #define LCD_CFG_MODE_SPECIAL_TFT_1	 (1 << LCD_CFG_MODE_BIT)
 #define LCD_CFG_MODE_SPECIAL_TFT_2	 (2 << LCD_CFG_MODE_BIT)
 #define LCD_CFG_MODE_SPECIAL_TFT_3	 (3 << LCD_CFG_MODE_BIT)
 #define LCD_CFG_MODE_NONINTER_CCIR656	 (4 << LCD_CFG_MODE_BIT)
 #define LCD_CFG_MODE_INTER_CCIR656	 (6 << LCD_CFG_MODE_BIT)
 #define LCD_CFG_MODE_SINGLE_CSTN	 (8 << LCD_CFG_MODE_BIT)
 #define LCD_CFG_MODE_SINGLE_MSTN	 (9 << LCD_CFG_MODE_BIT)
 #define LCD_CFG_MODE_DUAL_CSTN	 (10 << LCD_CFG_MODE_BIT)
 #define LCD_CFG_MODE_DUAL_MSTN	 (11 << LCD_CFG_MODE_BIT)
 #define LCD_CFG_MODE_SERIAL_TFT	 (12 << LCD_CFG_MODE_BIT)
...