JTAG Serial Cable run 1 for Milkymist One

Schedule

Item	Description	Planned Start date	Status
KiCad design file,			Done
KiCad to BOM	KiCad generates lst file		Done
KiCad to Digi-Key/Mouser/Sharism	boom generates shopping list / Order status	All parts get ordered.	Done
KiCad to gerber/drill file	The process of settings on KiCad Gerber and Drill Files		Done
Determine PCB panelized	http://en.qi-hardware.com/wiki/File:M1_jtag_panel_run1_illustration_revised.pdf, source.		Done
Single gerber-Out to PCB maker	check list, pcb maker sent a panel gerber file back		Done
KiCad to AI file	How to generate KiCad Automatic Insertion File? coordinate files（front /back ) of parts.		Done
PCB Back Check	Confirm PCB quality, panel top, panel bottom		Done
Engineering files to SMT manufacturer	BoM/AI/panel gerber/placement top/placement bottom/parts polarity top/released parts' qty information/page 58 of Soldering reflow profile in FT2232HQ-REEL	This date prior to SMT date	Done
Some photos SMT/Through hole process	PCBA is estimated arrival on January 3th, 2011	Within end week of 2010	Done
Tests & Results			Done

Some photos

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  SMT reflow machine's temperature profile for front & back side.

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  The P2 2x7pins JTAG header being placed manually. Notice that the package status of P2 incoming I chose is tubes. So there's no way to be picked/placed by auto machine. This is the case that was not an good design for manufacturing. It must be improved later on design beginnings and layout changes like choosing the part with locator posts if having further runs later.

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  The operator did the place work followed my instruction to her. This was escaped the foreword seriously if I didn't provide them an clear instruction on placing RIGHT at CENTER of pad of P2 footprint EXACTLY. I can imagine it should have made completed wrong and nonbalanced placement if I have not reminded.

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  I requested them that I would like be played a role as a quality check member who stands in the rear of her and in front of smt reflow machine to make sure the P2 at the right placement.

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  First panel with back side has been gone through smt reflow machine. I checked that they were good especially I satisfied the placement of P2.

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  Firstly we planed to mount back side of panel then front side. The serial female header 1x 4 pins of P1 was missing due to different process. We only planed to produce 100 pcs, so this P1 part will be manually soldered later. Notice that an optical Fiducial Mark placed above 'C35' Silkscreen this time is totally non-function since I leaved a width of 5mm only for V-Cut side board. But their smt machine FUJI XP-243E's conveyor blocked 3mm which covered this mark, so smt machine can not do an calibration of setting origin point. This happens since we changed smt vendor and got not enough info from different machine. This will always be paid more attentions on this. But we were lucky because we had have P1 though holes. So use P1's holes to be as the origin of the coordinates. So either placing the design/placement within 'single' gerber or shifting the mark a bit.

• 

  First panel with front side.

• 

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Tests and Results

• Step1: Make sure the pod works on a stable +5V supplied by mini-USB cable and its current is good without huge comsuptions. See Fig. 2. Finally got one board with D2 failure.

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  Fig. 1, To be tested

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  Fig. 2, Firstly make sure LED D2 is light and voltage and current are good.

• Step2:

Follow instructions of Update_JTAG_firmware_on_Windows. , use FTDI_Prog tool to update following data:

Vendor ID : 20B7
Product ID : 0713
Manufacturer : Qi Hardware
Product Description : MIlkymist One JTAG/Serial
Port A Hardware : 245 FIFO

The result of Step 2, got one board can not be detected in FTDI_Prog.

Links

• Milkymist JTAG-serial daughterboard
• http://www.milkymist.org/wiki/index.php?title=Flashing_the_Milkymist_One
• http://www.milkymist.org/wiki/index.php?title=JTAG
• Sharism prototype runs