GPS Free Stack/Notes About Namuru
Acknowledgments
Registers
(note some register are nor part of namuru upstream) /* CH */ CH0_PRN_KEY (0x00) Gold code sequence CH0_CARRIER_NCO (0x04) Local carrier oscilator frequency control CH0_CODE_NCO (0x08) Local C/A code oscilator frequency control CH0_CODE_SLEW (0x0c) C/A code delay control CH0_I_EARLY (0x10) I Early Accumulator CH0_Q_EARLY (0x14) Q Early Accumulator CH0_I_PROMPT (0x18) I Prompt Accumulator CH0_Q_PROMPT (0x1c) Q Prompt Accumulator CH0_I_LATE (0x20) I Late Accumulator CH0_Q_LATE (0x24) Q Late Accumulator CH0_CARRIER_MEASUREMENT (0x28) Carrier cycle count and phase since last TIC CH0_CODE_MEASUREMENT (0x2c) Code measurement (code half-chip, code NCO phase) CH0_EPOCH (0x30) C/A code count latched on TIC CH0_EPOCH_CHECK (0x34) same as EPOCH but no latched to TIC CH0_EPOCH_LOAD (0x38) Modify epoch counter CH0_ENABLES (0x3c) Enable logis register:
ch0_epoch_enable,ch0_slew_enable,ch0_prn_key_enable,ch0_prn_key_enable
/* Status */ STATUS (0x380) bit 0 TIC occurred, bit 1 accumulator int, need to be clean manually after read NEW_DATA (0x384) data dump one bit per channel TIC_COUNT (0x388) Provides TIC down counter value ACCUM_COUNT (0x38c) Provides ACCUM INT down counter value CLEAR_STATUS (0x390) Clear STATUS flags (need to be cleared) HW_ID (0x3bc)
/* Control */ RESET (0x3c0) Software reset (need to be cleared) PROG_TIC (0x3c4) Control TIC period value for down counter PROG_ACCUM_INT (0x3c8) Control ACCUM INT period (must be less 1 ms)
