GPS Free Stack
This page is intended to document about a free stack GPS/GNSS Software/Hardware Defined implementation for the Nanonote/Milkymist One using a SiGE RF IC.
Some front-end GPS RF ICs have open data-sheets, for example SE4120L, there are also open stack/software/hdl code developed to correlate GNSS-GPS raw data coming from a RF frontend.
Current goal is take advantage of exiting code (hdl and software) for gps signal processing and fit it a copyleft gps receiver solution.
Contents |
Alternative RF ICs
GPS L1 Front-end available in the market:
- SiGE SE4162T 4110L
- MAXIM MAX2769
- Atmel ATR0601
- ST STA5620
- Nemerix NJ1006
- Texas Instruments TRF5101
Software
All this software run and compile on gnu/linux systems (at least x86)
- GPS-SDR is proven to work with devices like gn3s/usrp
- OSGPS was designed to work with data from an old SiGE chip 4110L, GPS1A Dongle, so it may help the code seems portable too, can be even be used for offline processing.
- SoftGNSS, matlab code from Akos book about, offline processing real data type version,ported to octave.
- RTKlib (not GUI)
IP Cores
Namuru Correlator (Clone for Zarlink GP2021), that implemented in SoC inside a FPGA, this a very important component as this step demand specialized hardware not available in most embedded devices.
Already integrated in Milkymist SoC, two clock domains (because namuru must be synced with sample clock), just cross clock sync for ack (wishbone), board seems no crash after a 100000 r/w cycles,
Interfacing
Currently the SiGe SE4162T-EK is interfaced with the Milkymist One board trought the expasion connector as follows:
SE4162T-EK1 EVB Milkymist One J4 Pin 1 VBAT .................................... J21 Pin 3 3V3 J4 Pin 3 SYNC ------------------------------------ J21 Pin 7 A20 J4 Pin 4 DATA .................................... J21 Pin 9 A21 J4 Pin 5 CLK_OUT ------------------------------------ J21 Pin 5 B21 J4 Pin 8 GND .................................... J21 Pin 17 GND J5 ANT (to active GPS External Antenna)
SiGE EVB Jumper positions:
J1 2<->3 Fit J9 1<->2 FIT R4 0 = 0R
This setup allow the use of the on-board regulator (wich is not the internal LDO from SiGE chip). (LDO still need to be tested) (LNA still need to be tested)
Optional Debug Signals on EVB:
J4 Pin 10 Vdd (Expected 2V9~ in normal operation) J4 Pin ANT_DET (Expected 3V3~ When External ANT connected)}
Real Mode More generic mode, no relay single chip, not saying complex is not better, just lacking support in embedded gps related software so far?
R9 = 47K to R14.
SE4162
This is the current specification for the chip/EVB from SiGE:
Data output format: Serial 4-bit baseband I/Q pulse sync data
2.048 Msps 4-bit I/Q interleaved, pulse sync (8.192 Mhz) Positive Edge Clock
Frame Structure: Repeating sequence of SI MI SQ MQ Active high SYNC pulse aligns with SI Sample Rate: 2.048 MSPS
Sample clock output: 8.192 MHz
GPS data and clock load: 15pF max (Nanonote pin is about 5pf)
IF Filter Centre Freq: 2.556 MHz
IF Filter BW: 2.2 MHz
TCXO reference frequency: 16.384 MHz
Tolerance: ±1.5 ppm (Set tolerance and 2 reflows)
Temperature (-30 to +85° ±0.5 ppm)
HW1 can be set ‘low’ to switch real data output mode (2-bit real, parallel SIGN/MAG data at 2.556 MHz IF and 16.384 MHz sample clock, propietary block converter disabled).
Boards
SE4162T-EK1 Evaluation Board
Active GPS Atena, just on the Window (Second floor apartment)
mm1 sige
Schedule
| Item | Description | Planned Start date | Status |
|---|---|---|---|
| Debug SiGE EVB Signaling, Visual check of signal and electrical measurements | SiGE EVB, 100Mhz scope-meter, digital multimeter, spectrum analizer | 23 Oct 2010 | Done |
| Implement Three State buffer | CPLD, Computer, Xilinx Sofware | 7 Nov 2010 | Done |
| Data Acquisition | Basically dump raw data to a file | 24 Nov 2010 | Done |
| Bloat raw data before send to analize | Raw data need to be "bloated" in some way, in order to be verified | Done | |
| Migrate sige core to mm1 soc | This task took a LOT, after learn about wishbone, understand something about FIFOs, dig milkymist code.. refoce C basis kwnoledge and who knows more | Done | |
| Migrate dump/debug tool/utils as a rtems command | Some minor clean-up | In progress | |
| Implement Test Software for Namuru code | On hold for now, osgps is a focused way | Done | |
| Try borre matlab code in Octave | Another method for off-line processing. | Not started | |
| Try SoftOSGSP with recorded data | Another method for off-line processing. AFAIK that sampled data was complex, and osgps just support real | Done | |
| Port Namuru Baseband Correlator to Milkymist SoC | Namuru is a correlator like gp2021, for wich there is already made software | 24 Jul 2011 | Done |
| Port osgps to rtems/uclinux | osgps was developed to work with a gp2021 correlator, now namuru is ported, is its turn | In progress | |
| Implement Acquisition and Tracking Loops for namuru | in order to get telemetry | In progress |
Source Code
All code related HDL code https://github.com/kristianpaul/milkymist (this include acquisition and namuru IP cores)
Software side for test https://github.com/kristianpaul/softgpsreceiver (Is not more like flicknoise but was forked from it)
Be aware switch to gps-sdr-testing branch!!
SoftOSGPS https://github.com/kristianpaul/osgps (with some fixes and hacks for the SiGE 4162T ) Be aware this do not process complex data.
Raw Data
Arranged as QQII Interleaved
4 BitSign/mag I/Q Data
http://downloads.qi-hardware.com/people/kristianpaul/
