GPS Free Stack
This page is intended to document about a free stack GPS/GNSS Software/Hardware Defined implementation for the Nanonote/Milkymist One using a SiGE RF IC.
Some front-end GPS RF ICs have open data-sheets, for example SE4120L, there are also open stack/software/hdl code developed to correlate GNSS-GPS raw data coming from a RF frontend.
Current goal is take advantage of exiting code (hdl and software) for gps signal processing and fit it a copyleft gps receiver solution.
Contents |
Alternative RF ICs
GPS L1 Front-end available in the market:
- SiGE SE4162T 4110L
- MAXIM MAX2769
- Atmel ATR0601
- ST STA5620
- Nemerix NJ1006
- Texas Instruments TRF5101
Software
All this software run and compile on gnu/linux systems (at least x86)
- GPS-SDR is proven to work with devices like gn3s/usrp.
- OSGPS was designed to work with data from an old SiGE chip 4110L, GPS1A Dongle, so it may help the code seems portable too, can be used for offline processing.
Any good gps toolkit written in C? :-)
IP Cores
Namuru Correlator (Clone for Zarlink GP2021), that implemented in SoC inside a FPGA, this a very important component as this step demand specialized hardware not available in most embedded devices.
This currently been integrated in Milkymist SoC
Own implementation of data acquisition module, as this is device specific and just for debug purposes like off-line procesing.
Interfacing
Currently the SiGe SE4162T-EK is interfaced with the Milkymist One board trought the expasion connector as follows:
SE4162T-EK1 EVB Milkymist One J4 Pin 1 VBAT .................................... J21 Pin 3 3V3 J4 Pin 3 SYNC ------------------------------------ J21 Pin 7 A20 J4 Pin 4 DATA .................................... J21 Pin 9 A21 J4 Pin 5 CLK_OUT ------------------------------------ J21 Pin 5 B21 J4 Pin 8 GND .................................... J21 Pin 17 GND J5 ANT (to active GPS External Antenna)
SiGE EVB Jumper positions:
J1 2<->3 Fit J9 1<->2 FIT R4 0 = 0R
This setup allow the use of the on-board regulator (wich is not the internal LDO from SiGE chip). (LDO still need to be tested) (LNA still need to be tested)
Optional Debug Signals on EVB:
J4 Pin 10 Vdd (Expected 2V9~ in normal operation) J4 Pin ANT_DET (Expected 3V3~ When External ANT connected)
SE4162
This is the current specification for the chip/EVB from SiGE:
Data output format: Serial 4-bit baseband I/Q pulse sync data
2.048 Msps 4-bit I/Q interleaved, pulse sync (8.192 Mhz) Positive Edge Clock
Frame Structure: Repeating sequence of SI MI SQ MQ Active high SYNC pulse aligns with SI Sample Rate: 2.048 MSPS
Sample clock output: 8.192 MHz
GPS data and clock load: 15pF max (Nanonote pin is about 5pf)
IF Filter Centre Freq: 2.556 MHz
IF Filter BW: 2.2 MHz
TCXO reference frequency: 16.384 MHz
Tolerance: ±1.5 ppm (Set tolerance and 2 reflows)
Temperature (-30 to +85° ±0.5 ppm)
Data Acquisition
Off-Line processing
Mainly intended for debugging purposes like off-line processing of the received data, it implement a 8 bits shift register that is stored in a 2k buffer on the fpga, this is currently on the Milkymist SoC, Received data is saved to file on the on-board nor memory, allowing a max sample size of 17Mb to be recorded.
Data is analyzed using an adapted version of the osgps, so far, signals from some gps satellites has been confirmed, but not carrier phase can be tracked.
osgps after process raw sample http://downloads.qi-hardware.com/people/kristianpaul/sigeraw_2011_lun30may_21-27hrs.bin
visual aid from gpredict simulation in order to identify satellites at the time of the data recording
Note highest state from osgps is just 3.
Debugging
Analyzing signal output from the board in order to verify is signal characterization.
Clock and Sync
Sync and Data
Just Clock Signal
Just Sync Signal
Boards
SE4162T-EK1 Evaluation Board
Active GPS Atena, just on the Window (Second floor apartment)
mm1 sige
Schedule
| Item | Description | Planned Start date | Status |
|---|---|---|---|
| Debug SiGE EVB Signaling, Visual check of signal and electrical measurements | SiGE EVB, 100Mhz scope-meter, digital multimeter, spectrum analizer | 23 Oct 2010 | Done |
| Implement Three State buffer | CPLD, Computer, Xilinx Sofware | 7 Nov 2010 | Done |
| Data Acquisition | Basically dump raw data to a file | 24 Nov 2010 | Done |
| Bloat raw data before send to analize | Raw data need to be "bloated" in some way, in order to be verified | Done | |
| Migrate sige core to mm1 soc | Done | ||
| Migrate dump/debug tool/utils as a rtem command | Some minor clean-up | Done | |
| Implement Test Software for Namuru code | Done | ||
| Try borre matlab code in Octave | Another method for off-line processing. | Not started | |
| Try SoftOSGSP with recorded data | Another method for off-line processing. | Work in progress | |
| Port Namuru Baseband Correlator to Milkymist SoC | Namuru is a correlator like gp2021, for wich there is already made software | In progress |
Source Code
All code related HDL code https://github.com/kristianpaul/milkymist (this include acquisition and namuru IP cores)
Software side for test here https://github.com/kristianpaul/flickernoise (Is not more like flicknoise but was forked from it)
Be aware switch to gps-sdr branch!!
SoftOSGPS https://github.com/kristianpaul/osgps (with some fixes and hacks for the SiGE 4162T )
Raw Data
Arranged as QQII Interleaved
4 BitSign/mag I/Q Data
http://downloads.qi-hardware.com/people/kristianpaul/
References
Web links which point to source of information related with the project are linked next
