GPS Free Stack
This page is intended to document about a free stack GPS/GNSS Sofware Defined implementation for the nanonote using a SiGE RF IC.
Some front-end GPS RF ICs have open data-sheets, for example SE4120L, there are also open stack/software developed to correlate GNSS-GPS raw/navigation data and provide a fix point. But still missing documentation about data acquisition module part for chips like SE4120L and others.
Even there is already projects like Namuru, I/Q correlation and tracking systems implemented in FPGA , this a very important point as this step demand specialized hardware not available in embedded all devices.
Contents |
Alternative RF ICs
GPS L1 Front-end available in the market:
- SiGE SE4162T 4110L
- MAXIM MAX2769
- Atmel ATR0601
- ST STA5620
- Nemerix NJ1006
- Texas Instruments TRF5101
Software
All this software run and compile on gnu/linux systems (at least x86)
- GPS-SDR is proven to work with devices like gn3s/usrp
- OSGPS was designed to work with data from an old SiGE chip 4110L, so it may help the code seems portable too, but just read file not a port or gpio pin either, the last windows version seems proud to support live correlation.
Any good gps toolkit written in C? :-)
Cores
Own implementation of data acquisition module, as this is device specific.
Public and free code from Namuru FPGA GPS tracking module can be re-used.
Interfacing
Due Ben nanonote Xburst chip is not capable of support more than 2.4Mpbs of throughput for serial data, according to some tests made by Werner Almesberger. The SIE board was initially used to deploy in the FPGA, the logic to capture the "raw" I/Q data from SiGE EVB. Currently all the work is been ported on the Milkymist One board and rtems/flickernoise app as well as this is a platform targeted for future and current developments.
SIE Current Wiring Status:
Milkymist One <- SiGE EVB
SE4162T-EK1 EVB Milkymist One UCF J4 Pin 1 VBAT .................................... J21 Pin 3 3V3 J4 Pin 3 SYNC ------------------------------------ J21 Pin 7 A21 exp2 J4 Pin 4 DATA .................................... J21 Pin 9 B21 exp4 J4 Pin 5 CLK_OUT ------------------------------------ J21 Pin 5 A20 exp0 J4 Pin 8 GND .................................... J21 Pin 17 GND J5 ANT (to active GPS External Antenna)
SiGE EVB Jumper positions:
J1 2<->3 Fit J9 1<->2 FIT R4 0 = 0R
This setup allow the use of the on-board regulator (wich is not the internal LDO from SiGE chip). (LDO still need to be tested)
Optional Debug Signals on EVB
J4 Pin 10 Vdd (Expected 2V9~ in normal operation) J4 Pin ANT_DET (Expected 3V3~ When External ANT connected)
SiGE <-> Milkymist SoC
A GPS custom will be made in order to fit in the CSR bus part of the Milktmist SoC, proper documentation can be founded in the doc directory in the Verlog Source code, in general the GPS buffer and registers will be mapped.
RTEMS run currently on the Milkymist SoC, (Linux is on devlopment). A driver for the GPS core, plus custom comands and tasks will be developed.
SE4162
This is the current chip we are working on as the availability of a EVB from SiGE.
Data output format: Serial 4-bit baseband I/Q pulse sync data
2.048 Msps 4-bit I/Q interleaved, pulse sync (8.192 Mhz) Positive Edge Clock
Frame Structure: Repeating sequence of SI MI SQ MQ Active high SYNC pulse aligns with SI Sample Rate: 2.048 MSPS
Sample clock output: 8.192 MHz
GPS data and clock load: 15pF max (Nanonote pin is about 5pf)
IF Filter Centre Freq: 2.556 MHz
IF Filter BW: 2.2 MHz
TCXO reference frequency: 16.384 MHz
Tolerance: ±1.5 ppm (Set tolerance and 2 reflows)
Temperature (-30 to +85° ±0.5 ppm)
Debugging
Just to make sure not have problems at the time of interfacing the GPS EVB to world, is required first to visually analyze/check the signal output from the board and verify is signal characterization.
Clock and Sync
Sync and Data
Just Clock Signal
Just Sync Signal
Boards
SE4162T-EK1 Evaluation Board
Active GPS Atena, just on the Window (Second floor apartment)
SiGE EVB and SIE
mm1 sige
Schedule
| Item | Description | Planned Start date | Status |
|---|---|---|---|
| Debug SiGE EVB Signaling, Visual check of signal and electrical measurements | SiGE EVB, 100Mhz scope-meter, digital multimeter, spectrum analizer | 23 Oct 2010 | Done |
| Implement Three State buffer | CPLD, Computer, Xilinx Sofware | 7 Nov 2010 | Done |
| Data Acquisition | Basically dump raw data to a file | 24 Nov 2010 | Done |
| Bloat raw data before send to analize | Raw data need to be "bloated" in some way, in order to be verified | Done | |
| Migrate sige core to mm1 soc | Done | ||
| Migrate dump/debug tool/utils as a rtem command | Some minor clean-up may needed to make it work using the RTEMS Region Manager | Done | |
| Implement Control Processing | Recycle code grom osgps or gpl-gps | No started | |
| Try borre matlab code in Octave | Not started | ||
| Port Namuru Baseband Correlator to Milkymist SoC | Namuru is a correlator like gp2021, for wich there is already made software | In progress |
Source Code
All code related HDL code https://github.com/kristianpaul/milkymist
Software side for test here https://github.com/kristianpaul/flickernoise
Be aware switch to gps-sdr branch
Raw Data
Arranged as QQII Interleaved
4 BitSign/mag I/Q Data
http://downloads.qi-hardware.com/people/kristianpaul/
References
Web links which point to source of information related with the project are linked next
