GPS Free Stack

This page is intended for document about a free stack for GPS/GNSS Sofware Defined implementation for the nanonote using a SiGE RF IC

Some front-end GPS RF ICs have open data-sheets, for example SE4120L, there are also open stack/software developed to correlate GNSS-GPS raw data and provide a fix point. But still missing documentation about data acquisition module for chips like SE4120L and others and no software designed for embedded devices like the Ben.

Alternative RF ICs

GPS L1 Front-end available in the market

• SiGE SE4162T
• Zarlink GP2015
• MAXIM MAX2769
• Atmel ATR0601
• ST STA5620

Software

All this software run and compile on gnu/linux systems (at least x86)

• GPS-SDR is proven to work with devices like gn3s/usrp

• OSGPS was designed to work with data from an old SiGE chip 4110L, so it may help the code seems portable too, but just read file not a port or gpio pin either, the last windows version seems proud to support live correlation.

• RTKLIB not explored yet, but mentioned in the list,so deserves a check

Interfacing

Due Ben nanonote Xburst chip is not capable of support more than 2.4Mpbs of throughput for serial data, according for some tests made by Werner Almesberger. The SIE board was initially used to deploy in the FPGA, the logic to capture the "raw" I/Q data from SiGE EVB. Curently all the work is been ported on the Milkymist One board and rtems/flickernoise app as well.

SIE Current Wiring Status:

SIE <- SiGE EVB

   SE4162T-EK1 EVB                                           SIE                    FPGA
  J4 Pin 1 VBAT     .................................... J19 Pin 28 3V3
  J4 Pin 3  SYNC    ------------------------------------ J19 Pin 24 DIG 22         Pin 33
  J4 Pin 4  DATA    .................................... J19 Pin 22 DIG 20         Pin 35
  J4 Pin 5  CLK_OUT ------------------------------------ J19 Pin 20 DIG 18         Pin 40
  J4 Pin 8  GND     .................................... J19 Pin 26 GND
  J5 ANT  (to active GPS External Antenna)

SiGE EVB Jumper positions:

 J1 2<->3 Fit
 J9 1<->2 FIT
 R4 0 = 0R

This setup allow the use of the on-board regulator (wich is not the internal LDO from SiGE chip). (LDO still need to be tested)

Optional Debug Signals

  J4 Pin 10 Vdd  (Expected 2V9~ in normal operation)
  J4 Pin ANT_DET (Expected 3V3~ When External ANT connected)

Xburst <-> FPGA

FPGA in SIE share data and address bus with SDRAM, SIE Examples suggest a map FPGA as ram by help of EMC in Xbusrt. Then a 2048bit sram block is implemented in the fpga (in read-first write mode) arranged with a counter in order to behave like a ring buffer.

Milkymist One implementation will use J17 IO expansion connector, and the acquisition logic will be ported as a logic core slave on the CSR bus? (Why not wishbone??)

SE4162

This is the current chip we are working on as the availability of a EVB from SiGE.

Data output format: Serial 4-bit baseband I/Q pulse sync data

2.048 Msps 4-bit I/Q interleaved, pulse sync 
               __   __   __   __   __   __
DATA         _/SI\_/MI\_/SQ\_/MQ\_/SI\_/MI\
              \__/ \__/ \__/ \__/ \__/ \__/

               __                  __  
SYNC         _/  \________________/  \_____

               __   __   __   __   __   __
CLK_OUT      _/  \_/  \_/  \_/  \_/  \_/  \
(8.192 Mhz)          Positive Edge

Frame Structure: Repeating sequence of SI MI SQ MQ Active high SYNC pulse aligns with SI Sample Rate: 2.048 MSPS

Sample clock output: 8.192 MHz

GPS data and clock load: 15pF max (Nanonote pin is about 5pf)

IF Filter Centre Freq: 2.556 MHz

IF Filter BW: 2.2 MHz

TCXO reference frequency: 16.384 MHz

Tolerance: ±1.5 ppm (Set tolerance and 2 reflows)

Temperature (-30 to +85° ±0.5 ppm)

Debugging

Just to make sure not have problems at the time of interfacing the GPS EVB to world, is required first to visually analyze/check the signal output from the board and verify is signal characterization.

• 

  Clock and Sync

• 

  Sync and Data

• 

  Just Clock Signal

• 

  Just Sync Signal

Boards

• 

  SE4162T-EK1 Evaluation Board

• 

  Active GPS Atena, just on the Window (Second floor apartment)

• 

  SiGE EVB and SIE

Schedule

Item	Description	Planned Start date	Status
Debug SiGE EVB Signaling, Visual check of signal and electrical measurements	SiGE EVB, 100Mhz scope-meter, digital multimeter, spectrum analizer	23 Oct 2010	Done
Implement Three State buffer	CPLD, Computer, Xilinx Sofware	7 Nov 2010	Done
Data Acquisition	Basically dump raw data to a file	24 Nov 2010	Done
Bloat raw data before send to analize	Raw data need to be "bloated" in some way, in order to be verified		In progress
Correlate PRN code	PRN Codes are unique per satellite		No started
Study Namuru Tracking Code (verilog)	Namuru projected already started something similar project for GPS I/Q data processing	As soon as confirmed current acquisition process is OK	No started
Get navigation format	RINEX is posible format for sat navigation data	As soon as confirmed current acquisition process is OK	No started

Source Code

All code is here http://projects.qi-hardware.com/index.php/p/ben-gps-sdr/

Raw Data

Arranged as QQII Interleaved

4 BitSign/mag I/Q Data

http://downloads.qi-hardware.com/people/kristianpaul/

References

Web links which point to source of information related with the project are linked next

• GPS_Free_Stack/Web Links
• GPS_Free_Stack/Books