#milkymist IRC log for Tuesday, 2013-12-10

ysionneauvery pretty!15:27
ysionneauwhat software has been used to make this picture?15:30
lekernelhmm, don't remember atm (the design guys did it)17:12
lekernelI just remember it renders amazingly fast for a ray tracer, less than a minute17:13
wpwrakvery elegant design17:50
davidc__lekernel: what are the flash A / flash B buttons for? boot image selection?18:18
davidc__or for FX triggers?18:18
lekernelFX triggers. it's not *that* nerdy :)18:23
kristian1aulpretty and fresh indeed18:36
barmstrongthat looks awesome. very polished!18:40
rjolekernel: did you have a chance to look at the patches i sent? https://github.com/jordens/migen/compare/for-upstream20:32
larscI demand a refund: http://metafoo.de/mixxeo.jpg ;)21:17
ysionneauthis one is trying to escape21:26
lekernelrjo, got them, will check them out shortly. been very busy with other things lately.21:47
lekernellarsc, how does it stick? from the solder flux?21:49
lekernellarsc, did you fix the power problem by the way?21:50
larscdidn't try yet21:50
larscI think the resistor is soldered to one of the pads21:50
larscjust with the wrong end21:51
larscand the power issue is a bit strange anyway, sometimes it works just fine21:52
lekernelah, so it's actually missing from the R16 pads?21:52
lekernelI see. will send that pic to creotech.21:52
rjolekernel: thanks.21:54
lekernellarsc, is the power problem also happening on other computers?21:56
lekernelor with a hub? have you checked the power with a scope and see if there's a drop?21:56
larscI only tried shortly on two different laptops and what I was seeing is that the board would randomly reset itself during boot21:57
larscI'm only assuming that it is a power issue21:57
larscI'll try to actually get the board up and running next week21:58
larscgot too much stuff at work that still needs to be done before I go on vacation and I don't want to distract myself for now21:59
lekernelrjo, looking at the signed bug atm; seems the transfer of negative numbers between iverilog and python is buggy22:56
lekernela = Signal((3, True), reset=-4) ==> s.rd(a) returns -422:57
lekernela = Signal((4, True), reset=-4) ==> s.rd(a) returns 422:57
davidc__lekernel: there's a bug in value_bits_sign FWIW (* operator doesn't return a (bits, sign) tuple - just bits)22:57
davidc__lekernel: I think I have a patch, but I'm not 100% on whether I have the sign flag right for all cases :)22:58
lekernelall cases? result is signed if any operand is signed23:03
davidc__yeah, I had False, True, True; just wanted to make sure I understood exactly what value_bits_sign was returning23:03
lekernelproblem is in verilog or iverilog23:14
lekernelhttp://pastebin.com/PSLaSpEr not -423:14
lekernelxilinx fuse also prints 423:18
lekernelI wonder wtf the verilog standard came up with again this time ...23:19
lekernelhttp://pastebin.com/5395ZhyR gives the expected -4; so sign extension works - but they made an exception for constants?!23:21
lekernelah, got it23:34
lekernelthe "-X'sdY" syntax sets bit X in value Y, which may or may not be the sign bit23:35
lekernelsign extension with constants otherwise works. this is again an imbecilic thing to do, but at least it won't be hard to fix.23:35
lekernelwill do that tomorrow. gn8.23:37
--- Wed Dec 11 201300:00

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