| ysionneau | barmstrong: you can still publish in your blog which Migen SHA-1 you are using :) | 08:40 |
|---|---|---|
| lekernel | rjo, hi | 20:39 |
| lekernel | any ideas for better name for the size module? fiter/fslice/freversed are not that related to sizes ... | 20:39 |
| lekernel | *for a better name | 20:39 |
| lekernel | rjo, what is #Subsignal("iob" | 20:48 |
| lekernel | in lx9_microboard? | 20:48 |
| lekernel | rjo, vga(_out) should use the same signal names as in https://github.com/m-labs/migen/blob/master/mibuild/platforms/mixxeo.py#L69 | 20:50 |
| rjo | lekernel: "container" since these imeplement analogous functions to what python calls "emulating container types". | 20:54 |
| rjo | lekernel: or "bits.py" ? | 20:55 |
| lekernel | bitcontainer? :) | 20:56 |
| rjo | lekernel: sounds good | 20:57 |
| lekernel | can you send a rename patch? I have merged yours already | 20:57 |
| rjo | lekernel: will do. | 20:58 |
| rjo | lekernel: ah. that iob should not be commented out. | 20:58 |
| rjo | lekernel: in general, i think it is approriate to offer different "views" onto the same pins in a platform (like pmod and pmod_diff in lx9 microboard). do you agree? | 20:59 |
| rjo | lekernel: where is vga(_out)? | 20:59 |
| lekernel | also, I'm thinking about phasing out the period parameter in CRG_ as using lookup_request and adding platform commands in do_finalize (which was added later) is more powerful (also works with user CRGs) | 21:00 |
| lekernel | yes, having pmod + pmod_diff with the same pins sounds good | 21:01 |
| lekernel | but right now there's pmod0/pmod1 with pins (respectively) | 21:02 |
| lekernel | F15 F16 C17 C18 F14 G14 D17 D18 | 21:02 |
| lekernel | H12 G13 E16 E18 K12 K13 F17 F18 | 21:02 |
| lekernel | and the pmod_diff has pins | 21:02 |
| lekernel | F15 C17 F14 D17 H12 E16 K12 F17 | 21:02 |
| lekernel | F16 C18 G14 D18 G13 E18 K13 F18 | 21:02 |
| lekernel | why is the order mixed like that? | 21:03 |
| rjo | lekernel: good. also the try: except Constraint things should be refactored to look more like: if plat.is_allocated(..): platform.add_...() | 21:03 |
| rjo | lekernel: request pmod_diff if you want differential pins io and iob. pmod0 or pmod1 if you want the connectors dingle-ended. | 21:04 |
| rjo | single | 21:04 |
| lekernel | yes, but the pin order wildly differs. I would have expected pmod0 to be "F15 C17 F14 D17 H12 E16 K12 F17" (positive pins) and pmod1 "F16 C18 G14 D18 G13 E18 K13 F18". there's probably a reason for it, but it just looks strange atm. | 21:05 |
| lekernel | the python coding style is usually inclined towards trying doing things and then catching exceptions, instead of testing if the operation will work | 21:06 |
| lekernel | vga is in zedboard | 21:07 |
| rjo | lekernel: pmod0/1 is according to connector numbering. pmod_diff is according to differential signals on the fpga. afaik the pairing is fixed. isn't it? | 21:09 |
| lekernel | ah, yes, I see | 21:10 |
| rjo | lekernel: true. but i still think there could be a more readable way to do it... | 21:11 |
| rjo | lekernel: i'll send patches for the iob lx9, the bitcontainer and the vga. anything else? | 21:12 |
| lekernel | add period constraints instead of using the "period" argument of CRG_* | 21:13 |
| rjo | lekernel: sent patches to list | 21:33 |
| rjo | lekernel: a few thousand bytes to large. i guess you get moderator email. i didnt do rename recognition in format-patch... | 21:54 |
| lekernel | yes, accepted it onto the list | 21:55 |
| lekernel | committed, thanks | 21:56 |
| rjo | lekernel: just noticed that i somehow messed up the authorship of that one patch... | 22:00 |
| lekernel | hmm, yes | 22:01 |
| lekernel | do you want me to try and fix it? it's a small patch... | 22:02 |
| lekernel | (and such fixes are messy afaik) | 22:03 |
| rjo | lekernel: i don't care. | 22:03 |
| lekernel | ok | 22:03 |
| --- Wed Dec 4 2013 | 00:00 | |
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