#milkymist IRC log for Tuesday, 2013-12-03

ysionneaubarmstrong: you can still publish in your blog which Migen SHA-1 you are using :)08:40
lekernelrjo, hi20:39
lekernelany ideas for better name for the size module? fiter/fslice/freversed are not that related to sizes ...20:39
lekernel*for a better name20:39
lekernelrjo, what is #Subsignal("iob"20:48
lekernelin lx9_microboard?20:48
lekernelrjo, vga(_out) should use the same signal names as in https://github.com/m-labs/migen/blob/master/mibuild/platforms/mixxeo.py#L6920:50
rjolekernel: "container" since these imeplement analogous functions to what python calls "emulating container types".20:54
rjolekernel: or "bits.py" ?20:55
lekernelbitcontainer? :)20:56
rjolekernel: sounds good20:57
lekernelcan you send a rename patch? I have merged yours already20:57
rjolekernel: will do.20:58
rjolekernel: ah. that iob should not be commented out.20:58
rjolekernel: in general, i think it is approriate to offer different "views" onto the same pins in a platform (like pmod and pmod_diff in lx9 microboard). do you agree?20:59
rjolekernel: where is vga(_out)?20:59
lekernelalso, I'm thinking about phasing out the period parameter in CRG_ as using lookup_request and adding platform commands in do_finalize (which was added later) is more powerful (also works with user CRGs)21:00
lekernelyes, having pmod + pmod_diff with the same pins sounds good21:01
lekernelbut right now there's pmod0/pmod1 with pins (respectively)21:02
lekernelF15 F16 C17 C18 F14 G14 D17 D1821:02
lekernelH12 G13 E16 E18 K12 K13 F17 F1821:02
lekerneland the pmod_diff has pins21:02
lekernelF15 C17 F14 D17 H12 E16 K12 F1721:02
lekernelF16 C18 G14 D18 G13 E18 K13 F1821:02
lekernelwhy is the order mixed like that?21:03
rjolekernel: good. also the try: except Constraint things should be refactored to look more like: if plat.is_allocated(..): platform.add_...()21:03
rjolekernel: request pmod_diff if you want differential pins io and iob. pmod0 or pmod1 if you want the connectors dingle-ended.21:04
rjosingle21:04
lekernelyes, but the pin order wildly differs. I would have expected pmod0 to be "F15 C17 F14 D17 H12 E16 K12 F17" (positive pins) and pmod1 "F16 C18 G14 D18 G13 E18 K13 F18". there's probably a reason for it, but it just looks strange atm.21:05
lekernelthe python coding style is usually inclined towards trying doing things and then catching exceptions, instead of testing if the operation will work21:06
lekernelvga is in zedboard21:07
rjolekernel: pmod0/1 is according to connector numbering. pmod_diff is according to differential signals on the fpga. afaik the pairing is fixed. isn't it?21:09
lekernelah, yes, I see21:10
rjolekernel: true. but i still think there could be a more readable way to do it...21:11
rjolekernel: i'll send patches for the iob lx9, the bitcontainer and the vga. anything else?21:12
lekerneladd period constraints instead of using the "period" argument of CRG_*21:13
rjolekernel: sent patches to list21:33
rjolekernel: a few thousand bytes to large. i guess you get moderator email. i didnt do rename recognition in format-patch...21:54
lekernelyes, accepted it onto the list21:55
lekernelcommitted, thanks21:56
rjolekernel: just noticed that i somehow messed up the authorship of that one patch...22:00
lekernelhmm, yes22:01
lekerneldo you want me to try and fix it? it's a small patch...22:02
lekernel(and such fixes are messy afaik)22:03
rjolekernel: i don't care.22:03
lekernelok22:03
--- Wed Dec 4 201300:00

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