| lekernel | http://www.clifford.at/yosys/cmd_synth_xilinx.html | 13:40 |
|---|---|---|
| wpwrak | so that plus a placer/router plus wolfgang's tools would be a complete synthesis suite ? | 13:46 |
| lekernel | if it works... trying to compile it atm | 13:56 |
| lekernel | hmm, it didn't crash and produced a convicing netlist for softusb_rx | 14:04 |
| wpwrak | neat ! :) | 14:05 |
| larsc | 'it didn't crash' - ah, better than the xilinx tools already ;) | 14:06 |
| lekernel | ah, it doesn't support verilog parameters | 14:08 |
| lekernel | well at least not with the syntax module_name #(...) instance_name | 14:08 |
| lekernel | ah, no, the problem is float parameters | 14:11 |
| lekernel | which means you can't use e.g. PLLs | 14:11 |
| lekernel | it also chokes on byte-wide BRAM write enables (e.g. mem[minisoc_adr][7:0] <= minisoc_dat_w[7:0];) | 14:12 |
| wpwrak | details, details ... | 14:12 |
| lekernel | yeah, they should have used Migen FHDL as representation instead of wasting time on pesky and often pointless verilog details :) | 14:13 |
| lekernel | still looks relatively good tho | 14:17 |
| lekernel | ah, and of course, the famous lm32 clog2 also stops it | 14:23 |
| lekernel | as well as "case" within a generate statement | 14:24 |
| lekernel | generate + if + assign is also a problem | 14:26 |
| ysionneau | aouch, lots of problems | 14:31 |
| lekernel | seems there are no more though | 14:32 |
| lekernel | I think misoc has a chance to compile after those details are fixed | 14:32 |
| lekernel | also produces a netlist for navre :) | 14:36 |
| ysionneau | doesn't iverilog produce netlist as well? | 14:37 |
| Action: ysionneau is lost about what's missing for open source toolchain | 14:38 | |
| lekernel | no, it's full of bugs, incomplete, and unusable | 14:38 |
| lekernel | so, planahead can implement that netlist, gives 74MHz and 1679 LUTs | 14:41 |
| lekernel | getting the Xst hard numbers atm, but iirc they were like 85MHz and 1200 LUTs | 14:42 |
| lekernel | Xst: 83MHz / 980 LUTs | 14:44 |
| larsc | almost half | 14:45 |
| ysionneau | pretty cool it works :) | 14:47 |
| larsc | is it possible that xst uses more specialized cells for some of the logic? | 14:47 |
| ysionneau | ah maybe yes, like multipliers | 14:48 |
| lekernel | maybe it uses the FF CE/RST signals better | 14:48 |
| lekernel | there is no multiplier in navre | 14:49 |
| lekernel | but yes, yosys does not use the carry chains | 14:49 |
| lekernel | I can imagine this accounts for a fair bit of the bloat and slowdown | 14:50 |
| wpwrak | how's the run time ? | 15:00 |
| lekernel | yosys seems slightly faster (haven't measured) | 15:11 |
| larsc | navre seems to be one of his testcases https://github.com/cliffordwolf/yosys-bigsim/tree/master/softusb_navre | 15:25 |
| larsc | so no wonder it is working ;) | 15:26 |
| ysionneau | ahah | 15:34 |
| larsc | and he also has a zed board | 15:39 |
| lekernel | compiled a led blinker design with yosys, it does the right thing on the board | 15:40 |
| lekernel | output signal names are like "$auto$iopadmap.cc:163:execute$129" ... | 15:41 |
| larsc | yea, I noticed that too | 15:42 |
| larsc | so, as far as I can see the xilinx module only has support for simple flipflops and simple luts | 15:42 |
| lekernel | no RAMs? | 15:43 |
| larsc | It should I guess | 15:44 |
| larsc | but I don't see them | 15:44 |
| larsc | you used the synth_xilinx command right? | 15:49 |
| lekernel | yes | 15:53 |
| larsc | I really like the tab completion | 16:05 |
| larsc | it seems to map memory to a big mux | 16:06 |
| larsc | hm, abc stumbles over the verilog generated by the tool | 16:10 |
| larsc | ah, no, it's the blif file | 16:17 |
| lekernel | ...where "B" stands for "Berkeley". pretty usual behaviour from academic software :) | 16:19 |
| larsc | the blif standard doesn't seem to specify how to handle conflicts in the lut table, those are the best standards I guess | 18:55 |
| lekernel | what's a conflict in the lut table? | 18:58 |
| larsc | 1x = 1, x1 = 0 | 18:58 |
| larsc | what is 11? | 18:59 |
| larsc | what is the output for 11 | 18:59 |
| lekernel | wouldn't it be an error to have "1x = 1, x1 = 0" ? | 18:59 |
| larsc | it does not specify whether this is an error, or whether the first line or the last line takes precedence | 18:59 |
| larsc | I think it is useful to be able to overwrite a more generic setting | 19:02 |
| larsc | e.g. if you have n inputs and for all but one combination the output is 0, you could write xxxx = 0, 0001 = 1 | 19:03 |
| larsc | instead of having to specify every possible combination | 19:03 |
| larsc | on the other hand, maybe 0001 = 1 is enough | 19:03 |
| larsc | and it will assume that everything else should be 0 | 19:04 |
| larsc | hm, it looks as if there are problems inferring the clock for memories | 19:16 |
| larsc | and why would I get a mux which muxes between const 0 and const 1 | 19:19 |
| larsc | lekernel: have you been able to infer ram? | 19:30 |
| lekernel | haven't tried | 19:33 |
| lekernel | just saw it failed to parse the byte-wide WE and didn't try further | 19:33 |
| larsc | ok | 19:35 |
| --- Mon Dec 2 2013 | 00:00 | |
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