#milkymist IRC log for Sunday, 2013-12-01

lekernelhttp://www.clifford.at/yosys/cmd_synth_xilinx.html13:40
wpwrakso that plus a placer/router plus wolfgang's tools would be a complete synthesis suite ?13:46
lekernelif it works... trying to compile it atm13:56
lekernelhmm, it didn't crash and produced a convicing netlist for softusb_rx14:04
wpwrakneat ! :)14:05
larsc'it didn't crash' - ah, better than the xilinx tools already ;)14:06
lekernelah, it doesn't support verilog parameters14:08
lekernelwell at least not with the syntax module_name #(...) instance_name14:08
lekernelah, no, the problem is float parameters14:11
lekernelwhich means you can't use e.g. PLLs14:11
lekernelit also chokes on byte-wide BRAM write enables (e.g. mem[minisoc_adr][7:0] <= minisoc_dat_w[7:0];)14:12
wpwrakdetails, details ...14:12
lekernelyeah, they should have used Migen FHDL as representation instead of wasting time on pesky and often pointless verilog details :)14:13
lekernelstill looks relatively good tho14:17
lekernelah, and of course, the famous lm32 clog2 also stops it14:23
lekernelas well as "case" within a generate statement14:24
lekernelgenerate + if + assign is also a problem14:26
ysionneauaouch, lots of problems14:31
lekernelseems there are no more though14:32
lekernelI think misoc has a chance to compile after those details are fixed14:32
lekernelalso produces a netlist for navre :)14:36
ysionneaudoesn't iverilog produce netlist as well?14:37
Action: ysionneau is lost about what's missing for open source toolchain14:38
lekernelno, it's full of bugs, incomplete, and unusable14:38
lekernelso, planahead can implement that netlist, gives 74MHz and 1679 LUTs14:41
lekernelgetting the Xst hard numbers atm, but iirc they were like 85MHz and 1200 LUTs14:42
lekernelXst: 83MHz / 980 LUTs14:44
larscalmost half14:45
ysionneaupretty cool it works :)14:47
larscis it possible that xst uses more specialized cells for some of the logic?14:47
ysionneauah maybe yes, like multipliers14:48
lekernelmaybe it uses the FF CE/RST signals better14:48
lekernelthere is no multiplier in navre14:49
lekernelbut yes, yosys does not use the carry chains14:49
lekernelI can imagine this accounts for a fair bit of the bloat and slowdown14:50
wpwrakhow's the run time ?15:00
lekernelyosys seems slightly faster (haven't measured)15:11
larscnavre seems to be one of his testcases https://github.com/cliffordwolf/yosys-bigsim/tree/master/softusb_navre15:25
larscso no wonder it is working ;)15:26
ysionneauahah15:34
larscand he also has a zed board15:39
lekernelcompiled a led blinker design with yosys, it does the right thing on the board15:40
lekerneloutput signal names are like "$auto$iopadmap.cc:163:execute$129" ...15:41
larscyea, I noticed that too15:42
larscso, as far as I can see the xilinx module only has support for simple flipflops and simple luts15:42
lekernelno RAMs?15:43
larscIt should I guess15:44
larscbut I don't see them15:44
larscyou used the synth_xilinx command right?15:49
lekernelyes15:53
larscI really like the tab completion16:05
larscit seems to map memory to a big mux16:06
larschm, abc stumbles over the verilog generated by the tool16:10
larscah, no, it's the blif file16:17
lekernel...where "B" stands for "Berkeley". pretty usual behaviour from academic software :)16:19
larscthe blif standard doesn't seem to specify how to handle conflicts in the lut table, those are the best standards I guess18:55
lekernelwhat's a conflict in the lut table?18:58
larsc1x = 1, x1 = 018:58
larscwhat is 11?18:59
larscwhat is the output for 1118:59
lekernelwouldn't it be an error to have "1x = 1, x1 = 0" ?18:59
larscit does not specify whether this is an error, or whether the first line or the last line takes precedence18:59
larscI think it is useful to be able to overwrite a more generic setting19:02
larsce.g. if you have n inputs and for all but one combination the output is 0, you could write xxxx = 0, 0001 = 119:03
larscinstead of having to specify every possible combination19:03
larscon the other hand, maybe 0001 = 1 is enough19:03
larscand it will assume that everything else should be 019:04
larschm, it looks as if there are problems inferring the clock for memories19:16
larscand why would I get a mux which muxes between const 0 and const 119:19
larsclekernel: have you been able to infer ram?19:30
lekernelhaven't tried19:33
lekerneljust saw it failed to parse the byte-wide WE and didn't try further19:33
larscok19:35
--- Mon Dec 2 201300:00

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