| whitequark | hi folks | 13:58 |
|---|---|---|
| whitequark | anyone interested to talk about wolfgang's fpgatools? | 13:58 |
| wpwrak | planning to pick things up where he left off ? | 14:04 |
| whitequark | more or less | 14:05 |
| wpwrak | sounds like a great idea to me | 14:05 |
| Action: whitequark nods | 14:06 | |
| whitequark | I'd want to understand synthesis process better | 14:06 |
| whitequark | as I understand it now, it's verilog -> RTL -> bitstream | 14:07 |
| wpwrak | sebastien wrote something about it a while ago ... lemme search ... | 14:09 |
| wpwrak | http://lekernel.net/fpga_toolchain_talk.pdf | 14:11 |
| lekernel | whitequark, I'd suggest you use Migen for the RTL to netlist step | 14:14 |
| lekernel | the AST is much simpler than Verilog's | 14:14 |
| lekernel | there's some very draft code here https://github.com/nakengelhardt/mist and EDIF output for designs made entirely of instances is in Migen (and you can feed it to the Xilinx P&R) | 14:15 |
| lekernel | and you can, of course, run the Migen Verilog back-end to get Verilog netlists for free (nice for debugging) | 14:15 |
| whitequark | lekernel: interesting | 14:21 |
| GitHub91 | [NetBSD] fallen pushed 1 new commit to master: http://git.io/YqOlpA | 14:22 |
| GitHub91 | NetBSD/master 05cdb65 Yann Sionneau: First kernel to be able to print messages to UART console on Milkymist SoC | 14:22 |
| ysionneau | ohoh, if whitequark starts to work on fpga tool ... then we might get something working nice in a short time :) | 14:25 |
| ysionneau | good to know you are interested in fpga tools | 14:26 |
| whitequark | heh | 14:26 |
| Action: whitequark is reading lekernel's pdf | 14:26 | |
| whitequark | ok, I see | 14:32 |
| whitequark | it's very convenient that the process consists of self-contained stages | 14:33 |
| whitequark | so I could e.g. take netlists in EDIF and output bitstream while using someone else's synthesis tools (say migen). | 14:33 |
| whitequark | what would be a good (xilinx, I assume) fpga series, for which most bitstream details are known? | 14:34 |
| ysionneau | it seems most of wolfgang work has been done on small Spartan 6 fpgas | 14:35 |
| lekernel | yes, afaik xilinx bitstreams are better known than altera's | 14:35 |
| ysionneau | and he understood a big deal of the bitstream format, since he was able to generate working bitstreams with his tool | 14:36 |
| lekernel | some of the ISE interfacing work is already done with migen, you just have to add mode="mist" to the build function call to use the - currently extremely limited - synthesis support | 14:37 |
| whitequark | judging by his Makefiles he used x6slx9 | 14:39 |
| ysionneau | yes | 14:39 |
| whitequark | so this board will do fine - http://www.xess.com/shop/product/xula2-lx9/ - I want something small and not very expensive in case I kill it | 14:39 |
| whitequark | or this... http://papilio.cc/index.php?n=Papilio.PapilioPro | 14:47 |
| lekernel | I have a Papilio Pro | 14:48 |
| lekernel | would make it a tad easier to use your work if we have the same board :) | 14:49 |
| whitequark | papilio pro it is, then | 14:49 |
| wpwrak | a bit over-engineered (you don't need ram and i think you could load the bitstream over jtag as well). but it would probably be hard to find something simpler | 14:49 |
| whitequark | wpwrak: which one? | 14:49 |
| ysionneau | xiangfu was doing a very simple s6 board IIRC | 14:50 |
| ysionneau | but you have to do it yourself | 14:50 |
| lekernel | RAM is great :) you want a netbsd with 1080p framebuffer demo, right? | 14:50 |
| ysionneau | you cannot buy it | 14:50 |
| wpwrak | both actually :) | 14:50 |
| wpwrak | lekernel: heh ;-) | 14:50 |
| wpwrak | ysionneau: you could fab and sell them ;-) | 14:51 |
| whitequark | ysionneau: I'd prefer to have as few points of failure as possible :) | 14:51 |
| ysionneau | whitequark: I understand | 14:51 |
| whitequark | so, bitstream (binary) corresponds 1:1 to a floorplan (textual)? | 15:04 |
| whitequark | in fpgatools | 15:04 |
| ysionneau | AFAIK yes | 15:18 |
| GitHub32 | [migen] sbourdeauducq pushed 1 new commit to master: https://github.com/milkymist/migen/commit/cdabf34bee2022d9115213f87f71c4ed257e9bea | 16:49 |
| GitHub32 | migen/master cdabf34 Sebastien Bourdeauducq: flow/isd: update to new APIs | 16:49 |
| GitHub190 | [misoc] sbourdeauducq pushed 3 new commits to master: http://git.io/Riz5Vw | 23:37 |
| GitHub190 | misoc/master 96fcb35 Sebastien Bourdeauducq: Revert "framebuffer: reset VTG"... | 23:37 |
| GitHub190 | misoc/master f5ba0ac Sebastien Bourdeauducq: videomixer: select 1024x768 by default | 23:37 |
| GitHub190 | misoc/master 7496ba6 Sebastien Bourdeauducq: framebuffer: fix resynchronization after resolution change | 23:37 |
| --- Thu Nov 21 2013 | 00:00 | |
Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!