| lekernel | it's interesting how the spartan6 PLLs would "lock" on noise signals | 15:47 |
|---|---|---|
| lekernel | (and lose that "lock" a few milliseconds later, after generating the most glitchy clocks possible) | 15:47 |
| GitHub47 | [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/_RuzrA | 15:54 |
| GitHub47 | misoc/master 1582bad Sebastien Bourdeauducq: videomixer: filter PLL lock output | 15:54 |
| wpwrak | lekernel: if you look very carefully on their silicon masks, you'll see, next to the circuit that implements this feature, a little "FOR SEBASTIEN <3" | 16:29 |
| larsc | From Xilinx with Love | 16:35 |
| GitHub61 | [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/sE14bg | 18:02 |
| GitHub61 | misoc/master 34e8e8c Sebastien Bourdeauducq: dvisampler: update address CSR at end of DMA | 18:02 |
| GitHub61 | misoc/master a5d9f72 Sebastien Bourdeauducq: videomixer: check resolution and frame length | 18:02 |
| larsc | hm, should I be worried, I increased the width of several register but the FIFO count goes down... | 19:23 |
| wpwrak | did it go from 65535 to 0 ? or did it become negative ? :) | 19:31 |
| larsc | It went down by one | 19:31 |
| larsc | simulation still works | 19:32 |
| larsc | fpga still works as well and the DMA controller is back to 99.6% bus utilization | 19:38 |
| --- Thu Nov 14 2013 | 00:00 | |
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