#milkymist IRC log for Monday, 2013-11-11

AlarmSalut09:20
Alarmaujourdh'hui à l'instant t il ne pleut pas Soleil09:21
lekernel?09:21
aeris...09:25
wpwrakit's raining sunshine ? is that an optimist or pessimist view ? :)09:25
aerisNo, it's a sunshinning rain09:25
Alarmsorry i'm dizzy09:44
AlarmI'm wrong channel09:45
ysionneauaaah that's annoying the makefile does a bootstrap -c && botstrap -p && bootstrap each time12:22
ysionneauwhat a waste of time :(12:22
ysionneauthat's terribly slow on my virtual machine12:23
GitHub72[misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/daZ6cA16:56
GitHub72misoc/master 1549956 Sebastien Bourdeauducq: cpuif: add memories to csr.h16:56
GitHub72misoc/master 3ba9fbe Sebastien Bourdeauducq: videomixer: generate EDID16:56
lekernelof course, the nvidia driver and/or the x11 shitware ignores modes described using new edid methods when they are not also described with the old ones17:16
lekernele.g. if you describe 1024x768@60Hz using a "detailed timing", the linux graphics shitware stack will refuse to show it unless the bit is also set in "established timings". modes that cannot be set using established timings, e.g. 720p, work fine though.17:18
lekernelI hope it doesn't get worse than that ...17:20
larscis that the closed source driver?17:23
lekernelyes17:24
larsciirc the DRM framework as no such restriction17:25
lekernelI wonder what sort of software architecture can lead to such a behaviour17:25
larscit just collects every possible mode from all sources17:25
larscmaybe it's in the EDID spec or something17:26
larscbut yea, I wanted to write a tool which you pass in a set modes and which spits out a valid edid with the modes sets in all the possible sources17:27
lekernelall 6, including the two GTF variants? :-)17:28
larscwell, that's the plan17:29
lekernelbtw - is there a good algorithm for finding the best approximation x/y of a fraction X/Y with a < x < b and c < y < d?17:29
larscbrute force ;)17:30
lekernelyeah, that could work - I have a pretty small range17:31
larscif b-a is small enough17:31
lekernelbut it's ugly :)17:31
lekernelthere could be a reason for the nvidia driver behaviour17:55
lekernelit supports GPU scaling of established timing resolutions to higher resolutions17:55
lekerneleg if you set up edid with 720p, it'll still show 640x480 and 800x600 in nvidia-settings (but not in xrandr) and scale that up17:57
lekernelI guess it does the determination of the "scaled" modes using the edid established timing bits17:57
lekerneland the driver gets confused when a established timing mode is set as a detailed timing ...17:57
larschm, everybody seems to be using grey counters for async fifos, but that will fail if the faster domain does reads/writes in bursts, right?18:48
lekerneliirc no18:51
lekernelit will work18:51
lekernelhttp://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO2.pdf18:51
larscok thanks18:53
larscbut the reason why a grey counter works is because only one bit is changed at a time, but if the source domain counts faster than the target domain it is possible that more than one bit changes19:04
larsce.g. if I have grey 0 = (000), increment two time, which is 011. Then the target domain might see 010, which is 319:10
barmstronghave you guys seen chisel? https://chisel.eecs.berkeley.edu/19:27
barmstrongit reminds me of migen in some ways19:27
larschttp://asicdigitaldesign.wordpress.com/2007/06/01/synchronization-of-buses/ supports my claim19:29
lekernelthere's a trick that adds one bit to the counters and makes everything work, but it's been a long time since I coded it and I don't remember the details19:54
larscI found another paper from the same author which explains why it works fine19:55
larscIn my mental model I assume that the counter just jumps from 000 to 011, which could cause problems if bit 2 is sampled before bit 319:58
larscbut of course the counter is 010 inbetween19:58
larsc00119:59
larscI mean19:59
larscwhich means that the one of bit 3 has already propagated19:59
larscthe extra bit is just for full and empty checking, as far as I understand20:00
larscI think the "Grey counter style #2" FIFO from that paper is what you implemented in migen20:02
lekernelbarmstrong, yes, chisel is quite similar fundamentally20:02
barmstrongi think it's interesting that it does its own simulation. i feel like that'd look a lot like icarus20:12
lekernelwhat do you mean, own simulation?20:31
GitHub52[misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/N1638Q20:34
GitHub52misoc/master 132b6ce Sebastien Bourdeauducq: videomixer: set established timing bits in EDID20:34
GitHub52misoc/master c8da400 Sebastien Bourdeauducq: videomixer: compute best m/d value for pixel clock synthesizer20:34
larsclekernel: are you using the mmcm block?20:37
lekerneldcm_clkgen20:37
lekernelone of the rare things that the s6 got right. the serial interface is a little annoying, but I'm just bickering.20:38
larschere is my code for calculating d and m for the mmcm, but it looks similar to yours: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/clk/clk-axi-clkgen.c#n9120:40
larscbut it starts with selecting the valid min and max values for m and d20:42
larscbased on the datasheet specification for the valid clock speeds20:42
barmstronglekernel: i'm refering to this "Chisel can generate a high-speed C++-based cycle-accurate software simulator"21:13
lekernelah21:15
lekernelwell, migen FHDL to C or LLVM should be doable too21:16
lekernelthe question is why :) so far the very slow icarus solution has been fast enough21:16
lekernelyay, 720p works21:18
lekernel5388Mbps memory bandwidth, with only one channel :)21:18
lekernelI get FIFO overflows with the second. argh.21:22
ysionneau:)21:58
GitHub186[misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/hzvunA22:24
GitHub186misoc/master 593867b Sebastien Bourdeauducq: videomixer: add more video modes22:24
GitHub186misoc/master 69568ad Sebastien Bourdeauducq: videomixer: support resolution change at runtime22:24
--- Tue Nov 12 201300:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!