#milkymist IRC log for Sunday, 2013-11-10

rjofunny. lekernel got ~11GB/s DDR memory bandwidth on the m1. I am getting ~9GB/s on this puny LX9 microboard where the DDR data is only 16 bit wide (compared to 32 on the M1)...07:26
rjoread: 4800Mbps  write: 4288Mbps  all: 9088Mbps07:26
larscand it is running at the same clock rate?09:21
larscI think the b is bits not bytes09:28
lekernelrjo, hi09:31
lekernelrjo, the gateware only reports the number of transactions, and the bus width is hardcoded in the memtest software09:31
lekernelso if you didn't fix it, you actually have only half the reported bandwidth09:31
lekerneland yes, it's bits, not bytes09:32
lekernelthe bus width could be added to a memtest core CSR09:47
GitHub20[misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/4bW7bg09:55
GitHub20misoc/master 05944cf Robert Jordens: cpuif.py: add _ADDR and _SIZE defines for each register...09:55
GitHub20misoc/master 4fc301c Robert Jordens: common.mak: -Os instead of -O3, smaller bios (<32k)09:55
rjolekernel: i see. the remaining difference is then probably 83.7/75 MHz clock.11:04
rjolarsc: i was assuming bits11:04
lekernelhow much of the lx9 are you using?11:16
rjolekernel: ~75% for the m1-soc -dvi -fb +memtest11:34
rjolekernel: do you prefer me sending patches or would you like to cherry-pick/pull from a repository?11:35
lekernelpatches are great11:35
lekerneldo you intend to merge lx9 support directly into misoc?11:35
lekerneli.e. is that a platform you're serious enough about it that it's worth the extra bit of maintainance hassle11:37
rjolekernel: it gets ugly distinguishing the two in top.py.11:37
rjolekernel: there is really not much extra stuff.11:37
lekernelyour build.py patch has a test for lx9_microboard11:38
rjolekernel: yes. and that part in build.py11:39
rjolekernel: in the end, the lx9 specific stuff is very small: https://github.com/jordens/milkymist-ng/commit/886291532774d50b0f35b5aa5e9b869b8b97bdd111:39
lekernelI wonder if it would make sense to revamp the misoc build/integration system so it's easier to add extra platforms, possibly in external repositories11:40
rjolekernel: yes.11:40
rjolekernel: split misoclib from top.py/make.py11:40
lekerneldoes your SPI flash core memory-map the flash data?11:41
rjolekernel: yes. like norflash11:41
lekernelyou should be able to XIP the BIOS then11:41
lekernelit shouldn't be ridiculously slow thanks to the lm32 caches11:42
rjolekernel: thats the plan.11:42
rjoin terms of cycles it is actually not much slower than the parallel norflash.11:43
rjosomething like ~24 cycles for a random read if the clocks are matched.11:44
rjo... but the onboard jtag is the most inconvenient thing on that board.11:45
lekernelyou can already use misoclib without make.py/top.py11:52
lekernelthe problem is, you'll have to duplicate a bunch of code from make/top and the BIOS11:53
lekernelanother portability issue is the lm32_include.v file. a radical solution would be to rewrite the whole lm32 core in migen :)11:53
lekernel(jtag) have you tried urjtag?11:53
lekernelit works nicely for writing the nor flash. afaik there's no support for SPI though.11:54
rjolekernel: re code splitting: exactly11:55
rjolekernel: seen it, yes.11:56
GitHub24[misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/0ChNtw11:56
GitHub24misoc/master 31ec33d Robert Jordens: s6ddrphy: use shorter Instance argument notation...11:56
lekernelthanks for the patch11:56
rjolekernel: it would be great if the digilent bozos would just open up their atmel based jtag thingy...11:57
lekernelatmel based? yet another one? lol11:58
lekernelI thought they used ez-usb11:59
lekernelwell, you can always reflash that atmel thing... but yes, it wastes everyone's time.12:00
rjothat would be overkill ;)12:00
rjolekernel: i could imaging they even burned the fuses so that i can't reflash it.12:01
lekernelotoh... I'm not a big fan of ftdi chips since I looked at some code, and would prefer an AVR-based solution12:01
lekernel(for future FPGA boards)12:01
lekernelhow fast is that JTAG?12:01
rjolekernel: sure.12:04
rjolekernel: dunno. it claims to do the fpga programming at 4MHz.12:05
rjolekernel: but writing the flash is ~10 minutes.12:05
lekernelSPI flash writing (and particularly erasing) isn't fast12:06
lekernelit also could be that they simply assume the worst-case erasure time from the datasheet, instead of monitoring the flash status during an erase12:06
lekernelyou can easily get a 5x slowdown with that technique :)12:06
rjolekernel: the etherbone slave looks like it should work base on the simulation but i never tested it with hardware. would you accept it now or would you rather wait until something uses it?12:07
lekernelI'd rather commit only code that is actually used. every bit I add, I have to maintain.12:08
rjolekernel: oh yes. and they invented another flash loading technique (sfutil.exe) which goes some other route but uses the same hardware...12:08
lekernelbut it'd be very nice to have etherbone :)12:08
lekernelshould be much faster for quick debugging hacks than using adhoc LM32 C software and TFTP12:09
rjolekernel: i'll send etherbone anyway. you can ignore it if you like ;)12:13
lekernelwhat are the obstacles to testing it on the lx9?12:15
rjonot much. need to write some wrapper that passes the etherbone packets over wire.12:16
rjothe "ether" in that etherbone is not there yet. etherbone actually only specifies the serialized protocol.12:17
rjobut you could run it over serial12:17
lekernelit'd be nice to combine it with an Ethernet MAC that the CPU can use at the same time12:18
rjoyes. i have only seen that FX2 implementation.12:20
GitHub25[misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/f_3RRw12:22
GitHub25misoc/master de87149 Robert Jordens: common.mak: drop the echo from the version tag finding, did not work here, use python -c...12:22
rjoweird. github tells me i wrote those patches two days ago. back then i did not have any patches yet...12:22
rjoaight. i'm off. thanks for commiting!12:24
lekernelyou're welcome12:25
GitHub24[misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/Bg0jXA22:54
GitHub24misoc/master 75d25af Sebastien Bourdeauducq: cosmetic changes22:54
GitHub24misoc/master f5211af Sebastien Bourdeauducq: videomixer: add EDID manipulation routines22:54
larscah, right what I need :)23:28
--- Mon Nov 11 201300:00

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