rjo | funny. lekernel got ~11GB/s DDR memory bandwidth on the m1. I am getting ~9GB/s on this puny LX9 microboard where the DDR data is only 16 bit wide (compared to 32 on the M1)... | 07:26 |
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rjo | read: 4800Mbps write: 4288Mbps all: 9088Mbps | 07:26 |
larsc | and it is running at the same clock rate? | 09:21 |
larsc | I think the b is bits not bytes | 09:28 |
lekernel | rjo, hi | 09:31 |
lekernel | rjo, the gateware only reports the number of transactions, and the bus width is hardcoded in the memtest software | 09:31 |
lekernel | so if you didn't fix it, you actually have only half the reported bandwidth | 09:31 |
lekernel | and yes, it's bits, not bytes | 09:32 |
lekernel | the bus width could be added to a memtest core CSR | 09:47 |
GitHub20 | [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/4bW7bg | 09:55 |
GitHub20 | misoc/master 05944cf Robert Jordens: cpuif.py: add _ADDR and _SIZE defines for each register... | 09:55 |
GitHub20 | misoc/master 4fc301c Robert Jordens: common.mak: -Os instead of -O3, smaller bios (<32k) | 09:55 |
rjo | lekernel: i see. the remaining difference is then probably 83.7/75 MHz clock. | 11:04 |
rjo | larsc: i was assuming bits | 11:04 |
lekernel | how much of the lx9 are you using? | 11:16 |
rjo | lekernel: ~75% for the m1-soc -dvi -fb +memtest | 11:34 |
rjo | lekernel: do you prefer me sending patches or would you like to cherry-pick/pull from a repository? | 11:35 |
lekernel | patches are great | 11:35 |
lekernel | do you intend to merge lx9 support directly into misoc? | 11:35 |
lekernel | i.e. is that a platform you're serious enough about it that it's worth the extra bit of maintainance hassle | 11:37 |
rjo | lekernel: it gets ugly distinguishing the two in top.py. | 11:37 |
lekernel | yeh | 11:37 |
rjo | lekernel: there is really not much extra stuff. | 11:37 |
lekernel | your build.py patch has a test for lx9_microboard | 11:38 |
rjo | lekernel: yes. and that part in build.py | 11:39 |
rjo | lekernel: in the end, the lx9 specific stuff is very small: https://github.com/jordens/milkymist-ng/commit/886291532774d50b0f35b5aa5e9b869b8b97bdd1 | 11:39 |
lekernel | I wonder if it would make sense to revamp the misoc build/integration system so it's easier to add extra platforms, possibly in external repositories | 11:40 |
rjo | lekernel: yes. | 11:40 |
rjo | lekernel: split misoclib from top.py/make.py | 11:40 |
lekernel | does your SPI flash core memory-map the flash data? | 11:41 |
rjo | lekernel: yes. like norflash | 11:41 |
lekernel | you should be able to XIP the BIOS then | 11:41 |
lekernel | it shouldn't be ridiculously slow thanks to the lm32 caches | 11:42 |
rjo | lekernel: thats the plan. | 11:42 |
rjo | in terms of cycles it is actually not much slower than the parallel norflash. | 11:43 |
rjo | something like ~24 cycles for a random read if the clocks are matched. | 11:44 |
rjo | ... but the onboard jtag is the most inconvenient thing on that board. | 11:45 |
lekernel | you can already use misoclib without make.py/top.py | 11:52 |
lekernel | the problem is, you'll have to duplicate a bunch of code from make/top and the BIOS | 11:53 |
lekernel | another portability issue is the lm32_include.v file. a radical solution would be to rewrite the whole lm32 core in migen :) | 11:53 |
lekernel | (jtag) have you tried urjtag? | 11:53 |
lekernel | it works nicely for writing the nor flash. afaik there's no support for SPI though. | 11:54 |
rjo | lekernel: re code splitting: exactly | 11:55 |
rjo | lekernel: seen it, yes. | 11:56 |
GitHub24 | [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/0ChNtw | 11:56 |
GitHub24 | misoc/master 31ec33d Robert Jordens: s6ddrphy: use shorter Instance argument notation... | 11:56 |
lekernel | thanks for the patch | 11:56 |
rjo | lekernel: it would be great if the digilent bozos would just open up their atmel based jtag thingy... | 11:57 |
lekernel | atmel based? yet another one? lol | 11:58 |
lekernel | I thought they used ez-usb | 11:59 |
lekernel | well, you can always reflash that atmel thing... but yes, it wastes everyone's time. | 12:00 |
rjo | that would be overkill ;) | 12:00 |
rjo | lekernel: i could imaging they even burned the fuses so that i can't reflash it. | 12:01 |
lekernel | otoh... I'm not a big fan of ftdi chips since I looked at some code, and would prefer an AVR-based solution | 12:01 |
lekernel | (for future FPGA boards) | 12:01 |
lekernel | how fast is that JTAG? | 12:01 |
rjo | lekernel: sure. | 12:04 |
rjo | lekernel: dunno. it claims to do the fpga programming at 4MHz. | 12:05 |
rjo | lekernel: but writing the flash is ~10 minutes. | 12:05 |
lekernel | SPI flash writing (and particularly erasing) isn't fast | 12:06 |
lekernel | it also could be that they simply assume the worst-case erasure time from the datasheet, instead of monitoring the flash status during an erase | 12:06 |
lekernel | you can easily get a 5x slowdown with that technique :) | 12:06 |
rjo | lekernel: the etherbone slave looks like it should work base on the simulation but i never tested it with hardware. would you accept it now or would you rather wait until something uses it? | 12:07 |
lekernel | I'd rather commit only code that is actually used. every bit I add, I have to maintain. | 12:08 |
rjo | lekernel: oh yes. and they invented another flash loading technique (sfutil.exe) which goes some other route but uses the same hardware... | 12:08 |
lekernel | but it'd be very nice to have etherbone :) | 12:08 |
lekernel | should be much faster for quick debugging hacks than using adhoc LM32 C software and TFTP | 12:09 |
rjo | yep. | 12:10 |
rjo | lekernel: i'll send etherbone anyway. you can ignore it if you like ;) | 12:13 |
lekernel | what are the obstacles to testing it on the lx9? | 12:15 |
rjo | not much. need to write some wrapper that passes the etherbone packets over wire. | 12:16 |
rjo | the "ether" in that etherbone is not there yet. etherbone actually only specifies the serialized protocol. | 12:17 |
rjo | but you could run it over serial | 12:17 |
lekernel | it'd be nice to combine it with an Ethernet MAC that the CPU can use at the same time | 12:18 |
rjo | yes. i have only seen that FX2 implementation. | 12:20 |
GitHub25 | [misoc] sbourdeauducq pushed 1 new commit to master: http://git.io/f_3RRw | 12:22 |
GitHub25 | misoc/master de87149 Robert Jordens: common.mak: drop the echo from the version tag finding, did not work here, use python -c... | 12:22 |
rjo | weird. github tells me i wrote those patches two days ago. back then i did not have any patches yet... | 12:22 |
rjo | aight. i'm off. thanks for commiting! | 12:24 |
lekernel | you're welcome | 12:25 |
lekernel | bye | 12:25 |
GitHub24 | [misoc] sbourdeauducq pushed 2 new commits to master: http://git.io/Bg0jXA | 22:54 |
GitHub24 | misoc/master 75d25af Sebastien Bourdeauducq: cosmetic changes | 22:54 |
GitHub24 | misoc/master f5211af Sebastien Bourdeauducq: videomixer: add EDID manipulation routines | 22:54 |
larsc | ah, right what I need :) | 23:28 |
--- Mon Nov 11 2013 | 00:00 |
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