#milkymist IRC log for Tuesday, 2013-10-01

barmstronghmm, i wonder how hard it would be to add 'after' support to migen01:40
davidc__barmstrong: for the FSM?01:40
barmstrongwell, i'm thinking if i wanted to add verilog delays for simulation01:41
barmstrongfoo.eq(bar, after=2) -> foo <= bar after 201:43
barmstrongor something like that01:43
barmstrongi guess in verilog that's #2 or something. my verilog is super rusty :)01:44
davidc__shouldn't be too hard... but given that iverilog hangs on most migen output anyhow :P01:50
barmstrongwait, what?01:51
barmstrongi've been using iverilog with my design without too much issue so far01:51
barmstrongis there something specifically i should look out for?01:51
davidc__iverilog doesn't seem to settle properly01:53
davidc__in some cases01:53
barmstrongoh, hmm01:53
davidc__mostly involving things where a var is set in one place, then If(var) in the other01:53
davidc__barmstrong: it seems to work for small blocks, but hangs when you string a bunch into a pipeline; at least in our design it does02:03
davidc__I have a custom migen patch (not really primetime ready) that reorders statements / does some splitting / etc such that everything can be combined into a big always block that just runs to completion02:03
sb0barmstrong: what do you need those delays for, exactly?23:55
sb0I'd rather not have them. they are not synthesizable, cause confusion (see all those xilinx source codes with <=#1), and add a fair amount of complexity that I believe is unwarranted23:57
sb0complex designs like milkymist-ng are totally fine without them23:58
--- Wed Oct 2 201300:00

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