| GitHub164 | [milkymist-ng] sbourdeauducq pushed 3 new commits to master: http://git.io/tFeMAA | 06:08 |
|---|---|---|
| GitHub164 | milkymist-ng/master 52be94f Sebastien Bourdeauducq: videomixer: handle HPD | 06:08 |
| GitHub164 | milkymist-ng/master d0edb7e Sebastien Bourdeauducq: dvisampler: reset PLL at startup | 06:08 |
| GitHub164 | milkymist-ng/master a0f0285 Florent Kermarrec: lasmicon/multiplexer: fix rdcmdphase/wrcmdphase inversion | 06:08 |
| barmstrong | sb0: I just really like the idea. I've used verilog some before, but I write Python for my day job. I was excited to see what Migen could do. | 20:49 |
| barmstrong | sb0: I'm just going to try writing a cpu and then a small computer and then write a kernel for it | 20:49 |
| barmstrong | the good stuff :) | 20:49 |
| sb0 | what about rewriting LM32 with Migen? :) | 20:50 |
| barmstrong | That's tempting. I'm hacking out a DLX implementation to get my feet wet. | 20:51 |
| barmstrong | I wanted to try to make a MIPS next | 20:51 |
| barmstrong | lm32 has a lot of mips features, right? | 20:51 |
| sb0 | I'd say it's a bit simpler, doesn't have patent trolls behind it, can be implemented very well in FPGAs, and if well-done the Migen implementation could become the official CPU for milkymist-ng and get used in a bunch of stuff | 20:53 |
| sb0 | also, there's some work ongoing on direct Migen-to-EDIF synthesis | 20:53 |
| sb0 | and LM32 is the last big chunk of Verilog remaining in milkymist-ng, which would cause problems to get rid of Xst (and then the other ISE tools) | 20:54 |
| barmstrong | hmm. interesting :) | 20:54 |
| barmstrong | it looked like the opcodes were sort of mips-inspired | 20:54 |
| sb0 | and finally, you can always look at the original Verilog to help you | 20:55 |
| barmstrong | by the way, have you played with django much? specifically, the orm | 20:55 |
| sb0 | I think it's fair to say it's one of the most tested open source softcore CPUs... | 20:55 |
| barmstrong | there's some really magical stuff they do that i think might be interesting in migen, but i'm brand new to migen | 20:55 |
| barmstrong | so I could be totally off the mark | 20:55 |
| sb0 | no, I haven't touched Django much | 20:56 |
| sb0 | do you have a link/examples of those orm features? | 20:56 |
| barmstrong | huh, i hadn't thought of the verilog being there, but that's a good point | 20:56 |
| barmstrong | Sure, have a look at https://docs.djangoproject.com/en/dev/topics/db/models/ | 20:57 |
| barmstrong | there is an example there that transforms that definition into a sql table | 20:57 |
| barmstrong | they play some tricks with python's __get__ and I think a bit of metaclassing | 20:57 |
| sb0 | ah, yes, that | 20:58 |
| sb0 | I saw some code using that indeed. didn't know it was called orm. | 20:58 |
| sb0 | yes, that could be a nicer syntax for Migen record layouts | 20:59 |
| barmstrong | anyway, nice work with migen. I'm stoked that I can write all my unit tests in python | 20:59 |
| sb0 | thanks :) | 21:00 |
| barmstrong | if I come up with any specific improvements, I'll probably just submit pull requests :) | 21:01 |
| sb0 | please send a patch to the mailing list instead, it's easier to merge | 21:01 |
| barmstrong | ah, got it | 21:02 |
| --- Tue Sep 10 2013 | 00:00 | |
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