--- Thu Sep 5 2013 | 00:00 | |
mumptai | hi | 09:30 |
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mumptai | I'm currently pushing around parts on a pcb design | 09:30 |
mumptai | small spartan6, some periphery and memory | 09:31 |
mumptai | and i'm not really sure about the choice between external sdram and (fast) sram | 09:32 |
mumptai | memory capacity would be sufficient with both | 09:32 |
ysionneau | if sram chips aren't too much expensive, maybe use sram chips? | 09:32 |
ysionneau | it's really easier to control, and faster | 09:32 |
mumptai | but speaking bus&cpu wise, how "bad" is the added latency of the sdram? | 09:33 |
ysionneau | dunno :/ | 09:33 |
mumptai | the sram is actually cheaper | 09:34 |
mumptai | but it also requires a fair a amount of power (but so does the old sdram) | 09:34 |
sb0 | murphy doesn't want to go away. all mixxeo boards have been incorrectly fitted with the extra-sluggish -2 slowness grade of slowtan6 | 11:15 |
sb0 | this sounds like a lot of upcoming fun trying to meet timing with the ise shitware | 11:16 |
larsc | fun | 11:28 |
sb0 | other than that, they look good so far. two are completely assembled and the power supplies are OK. | 11:31 |
larsc | good | 11:33 |
GitHub18 | [migen] sbourdeauducq pushed 6 new commits to master: http://git.io/9CNDRw | 11:34 |
GitHub18 | migen/master 71b14ac Florent Kermarrec: actorlib: add fifo | 11:34 |
GitHub18 | migen/master 87a68ec Sebastien Bourdeauducq: examples/basic/namer: cleanup | 11:34 |
GitHub18 | migen/master 1209ec1 Sebastien Bourdeauducq: actorlib/fifo: rewrite... | 11:34 |
larsc | hm, what's typically the default pin configuration after power on reset, before loading the bitstream for xilinx fgpas? | 17:53 |
Hawk777 | larsc: tristated or pull-up, depending on the state of the HSWAP_EN pin | 19:22 |
larsc | thanks | 19:35 |
--- Fri Sep 6 2013 | 00:00 |
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