#milkymist IRC log for Thursday, 2013-07-25

davidc__lekernel: have you run into migen generated code that hangs iverilog [seems to be something about large sensitivity lists + non-blocking assignments in combinatorial code]08:40
lekernelyes, https://ssl.serverraum.org/lists-archive/devel/2012-November/003172.html08:51
lekernelother simulators have different behaviours ...08:52
lekerneland yeah, verilog/vhdl are that bad08:53
cdelekernel: what do you think about the free modelsim provided with altera? will it work with migen code?09:37
lekerneliirc modelsim has the same problem09:37
lekernelI also think it should not be too hard to fix in iverilog09:38
cdethanks. what about vhdl?09:38
lekernelbah, it can happen in either language, depending how the simulator implements this stupid event stuff09:39
cdeyes09:39
lekernelI haven't tried to reproduce it in vhdl09:39
lekernelbut I can imagine it's the same pain in the ass09:40
lekerneldavidc__, if you use the display_run option for verilog conversion I guess you will see that iverilog keeps running a loop of combinatorial always blocks, even though the signal values do not change anymore09:42
Last message repeated 1 time(s).09:57
davidc__lekernel: Ok; I'll check that out to try and narrow it down. I made a few minimal testcases; and it should be settling just fine15:46
davidc__[seems to be an issue where it should settle but doesn't]15:46
lekernelthe code from my email triggers the problem15:49
davidc__so maybe I'll investigate fixing iverilog15:49
lekerneleven though it settles15:49
davidc__lekernel: the other option could be to change to blocking assignments in combinatorial blocks; and split always blocks (magically; need to think more about the splitting)15:57
davidc__lekernel: That option might actually be preferable - some simulators can theoretically go a lot faster with that coding style15:57
GitHub61[migen] sbourdeauducq pushed 2 new commits to master: http://git.io/dr3paQ16:00
GitHub61migen/master b367932 Sebastien Bourdeauducq: fhdl: introduce module decorators16:00
GitHub61migen/master fcd48da Sebastien Bourdeauducq: examples/two_dividers: demonstrate InsertCE and InsertReset decorators16:00
GitHub2[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/Xrgssw16:00
GitHub2milkymist-ng/master 8e04de5 Sebastien Bourdeauducq: memtest/LFSR: use module decorators16:00
lekerneldavidc__, iirc there were issues with blocking assignments, even in comb blocks16:01
davidc__lekernel: blocking assignments wont result in the same code execution (can't retrigger same always block sensitivity list IIRC), so we'd need to split into multiple always blocks16:02
lekernelyes, I remember a similar mess when i tried that16:02
lekernelanother option is to ditch verilog entirely for simulation, but then you can't simulate legacy verilog modules anymore16:03
lekerneldirect EDIF output would also be a desirable feature ...16:04
lekernelthe only real problems with existing verilog code are LM32 and simulation models such as xilinx unisim, micron models, etc.16:05
davidc__lekernel: yeah :S. Anyhow; always-block-splitting looks to be possible for non-cyclic code [since combinatorial blocks should be a DAG]16:05
lekernelLM32 could be done relatively easily by rewritting in FHDL16:05
davidc__lekernel: eh; I run into a similar problem with my project. I have a bunch of verilog from earlier versions that I'd really rather not rewrite16:05
lekernelperhaps with some semi-automated tool16:06
lekernelunisim, micron models etc. are more of a problem since you don't want to track the bugs you may have introduced during the rewriting16:06
davidc__Anyhow; I'll look at always-block-splitting, moving to blocking ops and see if its possible. Having the datastructures you'd need for that wouldn't be terrible anyhow; you could use them for things like direct LLVM IR emission; for really fast simulators16:07
lekernelturning comb logic into clean DAGs is also a nice feature, since it's one step towards EDIF output :=16:07
lekernel:)16:07
lekernelit would potentially speed up simulations too. I found that iverilog runs the comb blocks way too many times with the current generated code.16:10
davidc__lekernel: yeah. People recommend only-blocking-assignments-in-combinatorial-blocks for that reason; but that requires reordering; or always-block splitting16:12
lekernelverilog is such a waste of time :) I wonder why people focus so much on simulation-only stuff like systemc instead of addressing those basic problems...16:14
GitHub0[migen] sbourdeauducq pushed 2 new commits to master: http://git.io/rGMuWA18:37
GitHub0migen/master b7ed19c Sebastien Bourdeauducq: fhdl: do not export Fragment18:37
GitHub0migen/master b96eb33 Sebastien Bourdeauducq: fhdl: compact Instance syntax18:37
ysionneauhum, mailing list max size for email is 40 kB, sorry about that20:14
GitHub80[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/_sCNWA22:39
GitHub80migen/master b8ff2f2 Robert Jordens: genlib/roundrobin.py: fix n==1 case22:39
--- Fri Jul 26 201300:00

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