#milkymist IRC log for Tuesday, 2013-07-16

davidc___lekernel: Hey; I think I've found a bug in AsyncFIFO - not sure if it is by design or not so I wanted to bounce it off you before submitting a patch15:20
davidc___lekernel: specifically; AsnycFIFO uses a synchronous read of the storage SRAM; which means that the read access pattern is:15:21
davidc___1. assert RE15:21
davidc___2. [readable changes if that was the last word in fifo]15:21
davidc___3. fifo.dout becomes valid15:21
davidc___whereas for a synchronous fifo; the pattern is 1. assert RE, 2 readable changes if necessary and fifo.dout changes to the new value15:22
lekernelyes, there's probably a bug in ayncfifo ;) I noticed it behaved strangely, haven't had time to look at it yet15:57
lekernelyour description could very well explain the problems I noticed16:02
GitHub5[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/fuQFhg16:20
GitHub5migen/master faa8b7c David Carne: fhdl/tools: clock domain merging for clock renaming16:20
davidc___lekernel: Ok. The easy fix is to just change the read-synchronous to read-asynchronous on that SRAM read port16:25
davidc___lekernel: but I'm not sure how that will affect your existing designs timing wise16:26
davidc___lekernel: Actually; maybe I'll create a patch with a 'tune' parameter that either designs the fifo with an asynchronous read; or with a synchronous read from consume_next [IIRC; don't have the source here]16:27
davidc___lekernel: so its right either way; but you can choose whichever is better timing-wise16:27
lekernelsynchronous read is always better; otherwise the memory can't be mapped to block RAM unless the synthesizer is smart enough to move a design's register into the memory16:31
lekernelso if you have a design with synchronous read, we use that and forget about the asynchronous one16:32
davidc___lekernel: I can fix it up tonight probably [+8h]16:32
davidc___lekernel: Also; I realized my patch from this morning doesn't fully solve clock domain renaming - for example; if you do {'foo':'bar', 'bar':'quux'}; its still nondeterministic depending on dict ordering [not to mention, what exactly is the intent of such a statement :)]16:33
davidc___Anyhow; I'll think about a better fix and send something to the list for comment16:34
lekernelyeah, python's non-deterministic dictionaries are a pain16:35
davidc___lekernel: BTW - do you prefer patches to the ML; pull requests to the ML; or just github pull requests? [or pull-req-via-irc ;)]16:40
lekernelpatches to ML16:40
lekernelwith git format-patch if possible16:40
davidc___Ok, will do.16:41
lekerneldavidc___, async_read fixed two bugs that have been bothering me for a while. thx ;)16:47
davidc___lekernel: no problem. I wrote a heinous workaround for the problem on my design then eventually decided "there's no way this can be by design... it has to be a bug"16:49
GitHub74[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/2nBxJQ16:54
GitHub74milkymist-ng/master 7e3b84a Sebastien Bourdeauducq: framebuffer: remove workaround for asyncfifo bug16:54
GitHub77[milkymist-ng] sbourdeauducq deleted asmi at 3240413: http://git.io/kkWhSg16:54
GitHub125[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/FWKg1g16:55
GitHub125migen/master 5b36f68 Sebastien Bourdeauducq: Remove ASMI16:55
larsc"Industrys First ASICclass All Programmable Architecture", hm whatever that means19:02
davidc___larsc: that we'll see it sometime around 204319:05
larscXilinx just anounced their series 8 with that headline19:06
larscwell 'just'19:07
davidc___larsc: heh; and the 7-series is still vaporware for most users19:12
larscyea, exactly my thought, the press release said 'available this year' and I though 'How about fixing 7-series first?'19:14
davidc___I mean; I've seen real 7-series chips (big kintex parts); but the Artix-7 SL / Artix-7 SLT parts don't actually exist AFAICT19:16
larscSL = slim?19:19
davidc___larsc: SL is just logic, no transceivers. They don't actually tell you what SL stands for; that wouldn't be market-droid-enough19:21
davidc___larsc: Also, all of the 7-series parts are BGA only19:21
davidc___which is understandable; but all the cheap devices are 0.8mm BGA or smaller19:22
davidc___so $$$ protos19:22
larscI have a couple of 7-series boards at work19:22
larschm, I wonder if the SLs are just ink on plastic19:30
davidc__larsc: on paper; you mean? :P19:40
larscyea that too, maybe the yield is just so good that they didn't need to label them as SLs ;)19:42
davidc__larsc: hah. Its more that the SL parts are smaller logic-wise19:46
davidc__I don't have huge logic designs; I just want my small designs to run faster :P19:46
davidc__Its just that dropping $130 on an XC7A100T [or $60 at volume / whatever it is] completely blows the BOM for most of the things I want to build with em19:47
davidc__Not to mention the cost of the 8 layer microvia board to route the damn thing out20:00
--- Wed Jul 17 201300:00

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