#milkymist IRC log for Sunday, 2013-07-14

azonenbergHawk777: is it non-copyleft open source?01:02
azonenbergMy entire SoC is BSD and i'm hoping to keep it that way01:02
azonenbergMy build system can optionally link with a GPL'd library and be dual-licensed01:03
azonenbergBut otherwise is pure BSD, all of the RTL is BSD too01:03
Hawk777azonenberg: not sure what GRLIBs license is; you should check it yourself. I dont need to know as Im only using it in stuff that will probably never be released anyway.07:44
azonenbergI see07:45
azonenbergI'll look into it07:45
azonenbergI need to learn more hard number-theory math anyway07:45
azonenbergand opencores has a complete lack of elliptic curve stuff last i looked07:45
azonenbergeven the RSA modules they had were horrible07:45
larscI think gems are rare on opencores in general08:21
azonenbergLol, true08:24
azonenbergthe last CPU i tried to use from there didn't even synthesize on the platform they said it was designed for :p08:24
lekernelread: 5075Mbps  write: 5195Mbps  all:10270Mbps15:17
lekernelnew memory controller on the M1 is starting to do quite good :)15:18
larscwhat were the previous numbers?15:56
mumptaiis that for a 16bit 333MHz DDR interface?17:15
lekernel32-bit but yes17:17
lekernel(166MHz clock)17:17
mumptaiwow, that pretty tight pipelining then ;)17:18
mumptaiis it using the mcb, or something homegrown?17:24
lekernelno xilinx IP whatsoever except the IOSERDES17:26
ysionneauno mcb17:26
lekernelall the rest is open source migen design17:26
lekernelI'm not even sure the MCB is that fast :)17:27
mumptaiioserdes was the 1/4 rate thingy?17:28
ysionneau17:17 < lekernel> read: 5075Mbps  write: 5195Mbps  all:10270Mbps < you are doing read and write "at the same time"?17:29
ysionneauI mean those numbers are obtained by doing read *and* write?17:29
ysionneauor just read and then just write17:29
lekernelno. but that controller would do some transaction reordering to group read and writes together to minimize bus turnaround times.17:30
ysionneaugreat!17:33
azonenberglekernel: the IOSERDES are not IP17:34
azonenbergthey're hard peripherals17:34
lekernelyeah, I know, hard IP if you prefer17:35
lekerneland you could do that with the fabric too - it's even faster xD http://hamsterworks.co.nz/mediawiki/index.php/Spartan_6_1080p17:35
azonenberglolwut?17:37
azonenbergIt's not faster17:37
azonenbergits a hackjob17:37
azonenbergif you read, the PLL jitter prevents it from being fully standard compliant17:38
lekernelyeah, don't get me started on slowtan6 PLL jitter. but that's a different problem, which you could workaround with an external PLL chip.17:38
azonenbergLol17:39
azonenbergOr use 7 series17:39
azonenbergHave you used 7 yet?17:39
lekernelno17:40
lekernelexcept running lm32 synthesis on vivado, which looked quite good. of course, maybe the bitstream it produced in so little time would not work when loaded ;)17:41
azonenberglol17:41
lekernelysionneau, goes down to 9169Mbps with simultaneous read/write17:46
ysionneaustill nice17:47
lekernelcould perhaps be optimized in a simple way by changing r/w switch decision thresholds, haven't tried17:47
ysionneauwhat do you mean by "all:10270Mbps" ?17:48
lekerneltotal data rate going into + out of the DRAM chips is 10270Mbps17:49
ysionneaubecause you're doing read and write at the same time during the same test17:49
lekernelI have a write core and a read core17:51
ysionneauare the results good for Mixxeo? for dual dvi input + vga output and maybe previsualization on two small LED screens ?17:51
lekernelI can run them simultaneously or not17:52
ysionneauok understood17:52
lekernelit'll be top-notch AMOLED :) finally got the german bureaucrats to ship them, yay!17:53
lekernelgetting the IO specification from I¬¬¬, on the other hand, is another problem17:53
lekernelworst case it should not be too hard to RE from the various bits of info they let slip17:54
ysionneau:)17:55
ysionneauso you think there will be enough ram bandwidth for all of this17:55
ysionneaumaybe trying to reduce the ram used by lm32 can save some bandwidth, by using small sleep loops entirely contained in the cache17:57
ysionneauand just serve interrupts17:57
lekernelyes, 720p will use 7G17:57
lekernellm32 is <200M even with a lot of cache misses17:58
lekernelalso, mixxeo will have 20% faster memory (DDR400 instead of DDR333)18:00
lekerneland a -3 slowtan6 that should run at 100MHz almost without excessive headache18:00
ysionneauso you will be able to access the DDR400 with a 200 MHz clock?18:02
lekernelyes18:02
lekernelhopefully18:02
ysionneauthat would be cool!18:03
GitHub51[milkymist-ng] sbourdeauducq pushed 2 new commits to master: http://git.io/wGKJiQ18:08
GitHub51milkymist-ng/master f3e07db Sebastien Bourdeauducq: software/memtest: basic test18:08
GitHub51milkymist-ng/master 2f662bf Sebastien Bourdeauducq: software/videomixer: fix overflow in memory bandwidth computation18:08
lekernelone of the most satisfying commit messages ever18:08
ysionneauvery tricky lurking bug?18:09
lekerneloverflow in memory bandwidth computation ;)18:09
ysionneauahah it was showing a very small number?18:10
ysionneau"why is my controller so slow?"18:10
lekernelit was showing garbage above a certain bandwidth :)18:11
GitHub100[linux-milkymist] larsclausen pushed 1 new commit to master: http://git.io/gs12YQ20:02
GitHub100linux-milkymist/master 4702860 Lars-Peter Clausen: lm32: Fix milkymist_timer_init prototype...20:02
GitHub46[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/3_N65g23:00
GitHub46milkymist-ng/master d753c52 Sebastien Bourdeauducq: lasmicon: fix FSM reset state with delayed_enter23:00
kristianpaulcould the mcb do it that fast?23:11
kristianpaulor that write/read troughput is getting closer to the built-in hw?23:11
--- Mon Jul 15 201300:00

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