#milkymist IRC log for Saturday, 2013-07-13

azonenberghttp://pastebin.com/EzCiqbi712:51
azonenberg:D :D :D :D :D12:51
azonenbergI created an xc2c32a bitstream that consists of a single NOT gate going from one FTDI GPIO pin to another12:52
azonenbergas well as breaking out both the original and inverted values to two LEDs12:52
azonenbergand successfully verified in hardware12:52
larscyeay :)12:53
azonenbergThe fitting has a lot of room for improvement and has //TODO's everywhere, and right now it only works with in-memory technology-mapped netlists12:53
azonenberghttp://redmine.drawersteak.com/projects/achd-soc/repository/revisions/1089/entry/trunk/tests/FCManualBitstreamGeneration/main.cpp#L20312:53
azonenbergas you can see i'm manually making netlist nodes in C++12:53
azonenbergIn technology-mapped form12:53
azonenbergI still have to reverse the bitstream config for the flipflops and global clocking12:54
azonenbergas well as improve my fitter in the event of routing conflicts (right now it just gives up)12:54
azonenbergIn parallel with that, i'm going to work on a technology mapper that goes from generic EDIF to this architecture12:54
azonenbergNo optimization for now, just make it work12:54
azonenbergThen see if i can hook iverilog up to that and run the same netlist all the way from verilog source to a bitstream12:55
azonenbergThen repeat for clocked logic12:55
azonenbergThen add a static timing analysis engine based on xilinx's published timing numbers (unlike for FPGAs, they actually publish the full speedfile data for the CPLDs in the datasheet... the FPGA timing characteristics in the datasheet do not include full details of routing delays)12:56
azonenbergAt that point i'll have a fully functional, but unoptimizing, toolchain12:56
larscwhich is still very nice12:59
azonenbergYeah13:00
azonenbergAnd room for improvement13:00
azonenbergRight now libcrowbar (the RE and synthesis stuff, CR-II only for now) is 4.4kloc of C++13:00
azonenberglibjtaghal, which includes the JTAG abstraction code, the logic for programming CR-II devices given a bitstream, and a lot of stuff for other device families, is 12.5kloc13:01
azonenbergAll BSD licensed and available from that redmine, but not officially released yet13:01
azonenbergi'm holding off on that until i hav esomething more stable13:01
lekernelazonenberg, what about migen-to-edif?13:46
azonenberglekernel: I want verilog support at some point13:46
azonenbergBut any open source tool that can generate EDIF would be a start13:47
lekernelwho really wants verilog :)13:47
azonenbergI like it :p13:47
azonenbergAnyway, i'm working bottom up13:47
azonenbergThe next step is to create some kind of EDIF file, probably by hand13:47
lekernelyou can get edif output from xst13:48
azonenbergand make a mapper that turns it into product term expressions and macrocells etc13:48
azonenbergI could do that too13:48
azonenbergI also have to figure out how to do constraint entry13:48
azonenbergcan you put constraints in EDIF?13:48
azonenbergi think not13:48
lekernelnot as far as I know13:48
azonenbergso i'd need a UCF or similar file13:48
azonenbergAnd if i was using iverilog, to support in-source constraints13:49
lekernelmigen to edif should really be quite straightforward imo... and you have a bunch of python tools13:49
azonenbergi'd need to modify it to export those constraints to a file along with the EDIF13:49
azonenbergI'd need to learn python first, lol13:49
lekernelplus a lot of "IP cores" that come with migen13:49
azonenberganyway, i first have to finish a lot of stuff in the fitting and bitstream generation stuff13:49
azonenbergi havent even RE'd the flipflop config fully13:49
azonenbergand there's a lot of corner cases like i mentioned in the fitter13:50
azonenbergand there's no mapper at all13:50
azonenbergBut the mapper will take in EDIF13:50
azonenbergThat's where i stop13:50
azonenbergany industry standard synthesis tool can make EDIF13:50
azonenbergAnd any open source one can be coaxed into generating it if you patch enough13:50
azonenbergSo i see no need to reinvent the wheel at that point13:51
azonenbergThe lower-level stuff is actually important13:51
azonenbergThough I would eventually like a BSD-licensed synthesis tool, iverilog is GPL13:51
azonenbergand you know how i feel about GPL :p13:51
azonenbergi'm all for open source but i want it to be a gift, not taken at gunpoint13:51
lekernelit doesn't work anyway13:52
azonenbergWhat doesn't work?13:53
azonenbergGPL?13:53
lekernelyeh13:53
lekernelanyway migen is bsd now, so that's another argument for it13:54
lekernel:)13:54
azonenbergLol, nice13:57
azonenbergBut i do want the ability to use existing verilog code eventually13:58
lekernelis there anything open source written in verilog that is worthy of being reused, except lm32 and a couple other things?13:59
lekernelmost of it is bitcoin miners lol13:59
azonenbergSome of my stuff, i'd like to think :p13:59
azonenbergAnd i'm continuing to write new verilog for my research13:59
azonenbergObviously we can't fit any of that on a CPLD13:59
azonenbergBut this will be a good foot in the door for F/OSS EDA14:00
azonenbergthen maybe wolfspraul (or someone else) can pick up fpgatools at some point and get that going14:00
azonenbergFrom what I see, btw, EDIF is a technology dependent format14:01
azonenbergas in, it describes cells rather than boolean logic expressions14:01
azonenbergSo i'd need to make a cell library for whatever synthesis tool was being targeted14:01
azonenbergI wonder if i could convince the synthesis tool to output mapped netlists for me :P14:02
azonenbergI doubt it14:02
azonenbergBut basically the synthesis tool would output something made of and/nand/nor/or/xor gates and flipflops14:03
azonenbergmy mapper would then squish all the combinatorial logic at each level into an and/or array with an optional xor at the end14:03
azonenbergoh also, on the topic of open source HDL14:04
azonenbergDoes anyone know of any open source elliptic curve signature schemes implemented for FPGA?14:04
azonenbergI'm specifically looking at signature verification using any elliptic curve scheme, signing will be done elsewhere14:04
azonenbergi just need a way to put a public key into my device and authenticate commands14:05
azonenbergi'm starting to do some fairly complex remote control stuff in my lab and i'd like at least some defense against random people sending packets to it :p14:05
azonenbergand although a HMAC is probably good enough for now, i will definitely need public key crypto eventually14:06
azonenberg(I also need it for my research)14:06
GitHub69[migen] sbourdeauducq pushed 2 new commits to master: http://git.io/nq_d_g15:16
GitHub69migen/master 6595b9a Sebastien Bourdeauducq: actorlib/spi/SingleGenerator: export CSRs15:16
GitHub69migen/master 65a0b12 Sebastien Bourdeauducq: actorlib/spi/DMAController: export length/storage/trigger15:16
GitHub58[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/eo-iGg15:16
GitHub58milkymist-ng/master 9ab22fe Sebastien Bourdeauducq: memtest/MemtestWriter: fix 'busy status stuck' bug15:16
GitHub119[linux-milkymist] larsclausen pushed 2 new commits to master: http://git.io/e2dgBQ16:40
GitHub119linux-milkymist/master 227108f Lars-Peter Clausen: lm32: Fix header file export...16:40
GitHub119linux-milkymist/master 5e45237 Lars-Peter Clausen: lm32: Use CLKSRC_OF for timer setup...16:40
Hawk777azonenberg: I think Aeroflex Gaislers open-source GRLIB has some elliptic curve crypto stuff in it.20:00
Hawk777GRECC: Elliptic Curve Cryptography Core20:01
--- Sun Jul 14 201300:00

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