#milkymist IRC log for Friday, 2013-06-14

GitHub1[milkymist-ng] sbourdeauducq pushed 2 new commits to asmi: http://git.io/atOCYw15:59
GitHub1milkymist-ng/asmi 3917ab4 Sebastien Bourdeauducq: videomixer: rescale pots15:59
GitHub1milkymist-ng/asmi d557a9a Sebastien Bourdeauducq: asmicon/bankmachine: fix full selector15:59
GitHub189[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/LM9C5A16:00
GitHub189migen/master 0c52c08 Sebastien Bourdeauducq: bus/asmibus: fix slot aging timer16:00
GitHub182[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/y3LYrg16:37
GitHub182migen/master ac2cde0 Sebastien Bourdeauducq: asmibus: remove port sharing16:37
GitHub169[milkymist-ng] sbourdeauducq pushed 2 new commits to asmi: http://git.io/NEQNQg16:37
GitHub169milkymist-ng/asmi b2319fd Sebastien Bourdeauducq: videomixer: support different resolutions16:37
GitHub169milkymist-ng/asmi 279a145 Sebastien Bourdeauducq: videomixer: add fb.c16:37
lekernelnew slowtan6 bug: 800x600 on both channels fucks up all PLLs, including the system clock one20:34
kristianpaulhow come?20:53
lekernelbecause no spartan6 feature works correctly, ever21:00
wpwrakmakes you wonder how the others fpgas are ...21:06
lekernelI had hopes for Tabula, but it turns out their software crashes way before reading the first byte of a HDL source file21:08
wpwrakdo you think the spartan thing is just a synthesis problem, or hardware ?21:09
lekernelit could be because I'm not using the GCLK pins to drive the PLLs...21:10
lekernelbut it looks hardware. works fine until a certain pixel clock frequency, then everything breaks down (including serial output)21:10
lekernelalso works if only one channel is active21:11
wpwrakhmm. could it be power ?21:13
lekernelfor some reason it doesn't happen in bios21:16
lekernelthe PLLs lock and everything looks normal there21:16
kristianpaulperhaps you dont wanna do it the xilinx way (hardware thing) ?21:20
kristianpaulhow are you driving the PLLs instead? ahh you using  exp connector ;) isnt?21:21
kristianpaulthat could explain part of it,21:22
kristianpaulwhy not use glck from memcard?21:22
kristianpauljust to give it a chance21:23
kristianpaulplay safe :)21:23
GitHub175[milkymist-ng] sbourdeauducq pushed 1 new commit to asmi: http://git.io/j-Bq1w21:40
GitHub175milkymist-ng/asmi cd910b8 Sebastien Bourdeauducq: videomixer: timeout on IDELAY busy21:40
GitHub178[milkymist-ng] sbourdeauducq pushed 3 new commits to master: http://git.io/RL742g21:42
GitHub178milkymist-ng/master bb43171 Sebastien Bourdeauducq: videomixer: support different resolutions21:42
GitHub178milkymist-ng/master 81d35ef Sebastien Bourdeauducq: videomixer: add fb.c21:42
GitHub178milkymist-ng/master 13bf6f5 Sebastien Bourdeauducq: videomixer: timeout on IDELAY busy21:42
davidc__lekernel: the PLLs are sourced from logic lines?21:57
lekerneldavidc__, it goes through the general interconnect22:01
davidc__Ah, yeah, Xilinx FPGAs really don't like when you do that22:03
davidc__lekernel: if you can; try hand-wiring a *CLK capable input to the clock signal22:04
davidc__and see if that fixes it22:04
lekernelI don't really understand why they don't like this22:06
lekernelis it because of jitter? internal crosstalk?22:06
lekernelduty cycle distortion?22:06
davidc__lekernel: Probably a combination of all of the above + black voodoo magic22:07
lekernelI don't believe in black voodoo magic :)22:10
davidc__lekernel: the occasional sacrifice is needed to get timing closure22:16
lekernelswearing seems to work too22:16
lekernelat least mine does22:16
lekernelthis is kinda frustrating, the picture with only 1 channel really looks clean in 800x600 now ...22:19
lekernelmaybe I should just wait for the mixxeo boards22:20
GitHub29[milkymist-ng] sbourdeauducq pushed 1 new commit to asmi: http://git.io/LuyN1g22:23
GitHub29milkymist-ng/asmi 3240413 Sebastien Bourdeauducq: top: better performance22:23
--- Sat Jun 15 201300:00

Generated by irclog2html.py 2.9.2 by Marius Gedminas - find it at mg.pov.lt!