#milkymist IRC log for Monday, 2013-06-10

lekernelhi _florent_08:58
lekernelI saw your problems with the IDDR clock frequency limit08:59
_florent_hi08:59
lekernelwhen you are using DDR mode, is it reasonably possible to use local clock inversion, or does this result in Xilinx-traditional massive skew and jitter?08:59
_florent_I don't know yet since for now I'm using SDR mode09:00
_florent_but with SDR mode I'm limited to 625 MHz09:01
_florent_the phy is now working at 600MHz09:01
lekernelif they did it right, but I'm not sure they did, using DDR mode should be as simple as setting the DDR parameter and having CLK0=clk, CLK1=~clk09:01
_florent_I've implemented the read & write leveling09:01
lekernelhm, are you using DQS for reading?09:02
_florent_I've tried that, but it was not working ;)09:02
lekernelok, sounds like slowtan6 then09:02
lekernelwhat happened?09:02
_florent_don't know exactly, I haven't simulated it, just that it was not working on board, I plan to simulate it09:02
lekernelbut the P&R didn't complain about unroutable clocks or such?09:03
_florent_IIRC it was able to route09:03
lekerneland then? what happened to the data?09:04
_florent_for the read leveling, I'm only using the bitslip + idelay, and I calibrate the bitslip + idelay by sampling the read pattern of the ddr09:05
_florent_don't remember for the DDR mode, it was really a quick test09:05
lekernelthat's not good, the DDR3 read timing with respect to the clock can vary by more than one bit time over PVT09:06
lekernelyou can do that with DDR, but with DDR2 the timing margin is very small, and it's negative with DDR309:07
_florent_I don't plan to run the phy at more than it is running now (DDR600)09:08
lekernelI wonder if some chips have random clk-data jitter that would make this always fail no matter the bitslip/idelay settings...09:08
lekernelwell it can work at 600Mbps/pin09:09
lekernelbut DDR3 is spec'd to 1600 :)09:09
lekernelthen you need to use DQS09:09
_florent_but if you have a little time to explain your solution with a schematic, I can try to implement it09:10
lekernelof course, thanks to the slowness of kintex, you'd only reach 1300 or so09:10
lekernelor try to overclock09:11
lekernelI'll try to post some document to the list...09:11
_florent_ok thanks09:11
juliusblekernel: did you get any further with your evaluation of the Tabula tools?15:37
lekernelnot really, their software won't compile any design due to bugs with subprocess management and lockfiles15:39
juliusb!!15:39
lekernelyeah, welcome to EDA-land15:39
juliusbyou get what you pay for ;)15:39
juliusbbut it really fails to do even an adder or something?15:40
lekerneldidn't they raise $108M in venture capital lately?15:40
lekernelthe HDL compiler won't even begin to read the source, it crashes before15:40
larscwe should try to do that too (raise a couple of millions of vc)15:42
juliusb108mil don't go far when you make chips15:44
larsclekernel: you do your con man trick and the money will flow in15:44
lekernelphew15:44
lekernelit's overrated15:44
lekerneleven academia can make chips15:44
larscjuliusb: but it's sufficient for one or two parties ;)15:45
lekernelor bitcoin miners15:45
juliusbthe things academia make are not intended to compete in a market place, and so are many nodes behind cutting edge15:45
juliusbalso not intended for mass production15:46
wpwraklarsc: that's the first viable plan for actually making money with the things we do ! :)15:46
Fallenoumake a lot of parties, they will need a lot of VJ equipments15:48
Fallenouthat's where we kick in15:48
lekernelhaha15:49
lekernelI could try actually15:49
wpwrakthe kickstarter party project  :)15:57
larscah tabula is that TDM FPGA company15:58
lekernelactually, due to some improbable incident I'm invited to one of those "high level" meetings next week that rejon would love. it is, of course, a BS-heavy environment and I'm not quite sure what to say there as I'm not working with the internet of things, the technological singularity, etc.16:07
wpwrakvisit the nearest buzzword generator, collect and remember a few pompous expressions, and you'll be fine16:08
lekernelmaybe I'd rather stay home and code or start to reverse engineer that turbomolecular pump I got from the trash a couple days ago16:08
wpwrakwhen people don't understand, they're often afraid to ask16:08
wpwrakthink of the buffet ! :)16:09
larscto paraphrase edison: We often miss opportunities because they are dressed in suits and look like boring social events ;)16:17
wpwrakthe philosophical revenge of the working class ;-)16:18
GitHub88[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/odocnA16:54
GitHub88migen/master 932bfa7 Sebastien Bourdeauducq: bus: Wishbone -> LASMI bridge (untested)16:54
GitHub115[migen] sbourdeauducq pushed 1 new commit to master: http://git.io/SDYiDg20:32
GitHub115migen/master 3a284b9 Sebastien Bourdeauducq: actorlib: LASMI DMA (untested)20:32
GitHub119[migen] sbourdeauducq pushed 2 new commits to master: http://git.io/fU1ArQ20:51
GitHub119migen/master aea3b59 Sebastien Bourdeauducq: genlib/fsm: fix handling of zero delayed_enter20:51
GitHub119migen/master fe54c68 Sebastien Bourdeauducq: lasmi: fix minor problems20:51
larscwhat does the L stand for btw?21:08
lekernellightweight21:09
larscwhat does it make lightweight21:17
wpwrakthe heavy thrusters ? ;-)21:18
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