| lekernel | hi _florent_ | 08:58 |
|---|---|---|
| lekernel | I saw your problems with the IDDR clock frequency limit | 08:59 |
| _florent_ | hi | 08:59 |
| lekernel | when you are using DDR mode, is it reasonably possible to use local clock inversion, or does this result in Xilinx-traditional massive skew and jitter? | 08:59 |
| _florent_ | I don't know yet since for now I'm using SDR mode | 09:00 |
| _florent_ | but with SDR mode I'm limited to 625 MHz | 09:01 |
| _florent_ | the phy is now working at 600MHz | 09:01 |
| lekernel | if they did it right, but I'm not sure they did, using DDR mode should be as simple as setting the DDR parameter and having CLK0=clk, CLK1=~clk | 09:01 |
| _florent_ | I've implemented the read & write leveling | 09:01 |
| lekernel | hm, are you using DQS for reading? | 09:02 |
| _florent_ | I've tried that, but it was not working ;) | 09:02 |
| lekernel | ok, sounds like slowtan6 then | 09:02 |
| lekernel | what happened? | 09:02 |
| _florent_ | don't know exactly, I haven't simulated it, just that it was not working on board, I plan to simulate it | 09:02 |
| lekernel | but the P&R didn't complain about unroutable clocks or such? | 09:03 |
| _florent_ | IIRC it was able to route | 09:03 |
| lekernel | and then? what happened to the data? | 09:04 |
| _florent_ | for the read leveling, I'm only using the bitslip + idelay, and I calibrate the bitslip + idelay by sampling the read pattern of the ddr | 09:05 |
| _florent_ | don't remember for the DDR mode, it was really a quick test | 09:05 |
| lekernel | that's not good, the DDR3 read timing with respect to the clock can vary by more than one bit time over PVT | 09:06 |
| lekernel | you can do that with DDR, but with DDR2 the timing margin is very small, and it's negative with DDR3 | 09:07 |
| _florent_ | I don't plan to run the phy at more than it is running now (DDR600) | 09:08 |
| lekernel | I wonder if some chips have random clk-data jitter that would make this always fail no matter the bitslip/idelay settings... | 09:08 |
| lekernel | well it can work at 600Mbps/pin | 09:09 |
| lekernel | but DDR3 is spec'd to 1600 :) | 09:09 |
| lekernel | then you need to use DQS | 09:09 |
| _florent_ | but if you have a little time to explain your solution with a schematic, I can try to implement it | 09:10 |
| lekernel | of course, thanks to the slowness of kintex, you'd only reach 1300 or so | 09:10 |
| lekernel | or try to overclock | 09:11 |
| lekernel | I'll try to post some document to the list... | 09:11 |
| _florent_ | ok thanks | 09:11 |
| juliusb | lekernel: did you get any further with your evaluation of the Tabula tools? | 15:37 |
| lekernel | not really, their software won't compile any design due to bugs with subprocess management and lockfiles | 15:39 |
| juliusb | !! | 15:39 |
| lekernel | yeah, welcome to EDA-land | 15:39 |
| juliusb | you get what you pay for ;) | 15:39 |
| juliusb | but it really fails to do even an adder or something? | 15:40 |
| lekernel | didn't they raise $108M in venture capital lately? | 15:40 |
| lekernel | the HDL compiler won't even begin to read the source, it crashes before | 15:40 |
| larsc | we should try to do that too (raise a couple of millions of vc) | 15:42 |
| juliusb | 108mil don't go far when you make chips | 15:44 |
| larsc | lekernel: you do your con man trick and the money will flow in | 15:44 |
| lekernel | phew | 15:44 |
| lekernel | it's overrated | 15:44 |
| lekernel | even academia can make chips | 15:44 |
| larsc | juliusb: but it's sufficient for one or two parties ;) | 15:45 |
| lekernel | or bitcoin miners | 15:45 |
| juliusb | the things academia make are not intended to compete in a market place, and so are many nodes behind cutting edge | 15:45 |
| juliusb | also not intended for mass production | 15:46 |
| wpwrak | larsc: that's the first viable plan for actually making money with the things we do ! :) | 15:46 |
| Fallenou | make a lot of parties, they will need a lot of VJ equipments | 15:48 |
| Fallenou | that's where we kick in | 15:48 |
| lekernel | haha | 15:49 |
| lekernel | I could try actually | 15:49 |
| wpwrak | the kickstarter party project :) | 15:57 |
| larsc | ah tabula is that TDM FPGA company | 15:58 |
| lekernel | actually, due to some improbable incident I'm invited to one of those "high level" meetings next week that rejon would love. it is, of course, a BS-heavy environment and I'm not quite sure what to say there as I'm not working with the internet of things, the technological singularity, etc. | 16:07 |
| wpwrak | visit the nearest buzzword generator, collect and remember a few pompous expressions, and you'll be fine | 16:08 |
| lekernel | maybe I'd rather stay home and code or start to reverse engineer that turbomolecular pump I got from the trash a couple days ago | 16:08 |
| wpwrak | when people don't understand, they're often afraid to ask | 16:08 |
| wpwrak | think of the buffet ! :) | 16:09 |
| larsc | to paraphrase edison: We often miss opportunities because they are dressed in suits and look like boring social events ;) | 16:17 |
| wpwrak | the philosophical revenge of the working class ;-) | 16:18 |
| GitHub88 | [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/odocnA | 16:54 |
| GitHub88 | migen/master 932bfa7 Sebastien Bourdeauducq: bus: Wishbone -> LASMI bridge (untested) | 16:54 |
| GitHub115 | [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/SDYiDg | 20:32 |
| GitHub115 | migen/master 3a284b9 Sebastien Bourdeauducq: actorlib: LASMI DMA (untested) | 20:32 |
| GitHub119 | [migen] sbourdeauducq pushed 2 new commits to master: http://git.io/fU1ArQ | 20:51 |
| GitHub119 | migen/master aea3b59 Sebastien Bourdeauducq: genlib/fsm: fix handling of zero delayed_enter | 20:51 |
| GitHub119 | migen/master fe54c68 Sebastien Bourdeauducq: lasmi: fix minor problems | 20:51 |
| larsc | what does the L stand for btw? | 21:08 |
| lekernel | lightweight | 21:09 |
| larsc | what does it make lightweight | 21:17 |
| wpwrak | the heavy thrusters ? ;-) | 21:18 |
| --- Tue Jun 11 2013 | 00:00 | |
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