| GitHub137 | [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/TdhRug | 14:16 |
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| GitHub137 | migen/master bac62a3 Sebastien Bourdeauducq: Make memory ports part of specials... | 14:16 |
| GitHub156 | [milkymist-ng] sbourdeauducq pushed 4 new commits to master: http://git.io/dcROOg | 14:17 |
| GitHub156 | milkymist-ng/master fb3e612 Sebastien Bourdeauducq: Use new memory port API | 14:17 |
| GitHub156 | milkymist-ng/master fdb021c Sebastien Bourdeauducq: dvisampler: increase frequency of reports to avoid missing WER values | 14:17 |
| GitHub156 | milkymist-ng/master 701aac2 Sebastien Bourdeauducq: bios/linker.ld: flash -> rom | 14:17 |
| _florent_ | Hi | 15:26 |
| _florent_ | the Kintex7 DDR Phy + ASMICON is working ;) (at least Memtest is Ok) | 15:26 |
| _florent_ | I'm using quarter rate commands : 200MHz mem clk and 50MHz command clk | 15:27 |
| _florent_ | Read & Write leveling are not implemented but I will probably try to add it to run at higher frequencies. | 15:27 |
| _florent_ | I'm now trying to run the ASMICON's ports at a multiple of the command frequency (to be able to run the CPU at more than 50 MHz...) | 15:27 |
| _florent_ | I've added some clock enable logic in the ports, but I have a question about clock domains definition with migen: | 15:28 |
| _florent_ | - Each Asmicon port will have it's own clock domain (a multiple or not of the command frequency), let say it use "sys_clk" for now | 15:28 |
| _florent_ | - Asmicon is using "asmicon_clk" | 15:28 |
| _florent_ | My first attempt was to pass the clock_domain in the port parameter and use self.add_submodule(new_port, {"sys": clock_domain} in the get_port function | 15:29 |
| _florent_ | and use self.add_submodule(self.asmicon, {"sys": "asmicon"}) in the top | 15:29 |
| _florent_ | But it seems the clock_domain renaming in the top is also renaming the port (since I'm using sys_clk for the port) | 15:29 |
| _florent_ | lekernel: do you have an idea on how to do it? | 15:29 |
| lekernel | great! | 15:34 |
| lekernel | so you have 1:4 serialization for the commands, right? | 15:35 |
| lekernel | and 1:8 for data | 15:35 |
| _florent_ | yes like your were saying the other day | 15:36 |
| _florent_ | it was easier in fact | 15:36 |
| lekernel | excellent | 15:36 |
| _florent_ | and I'm using 4 phases | 15:36 |
| lekernel | with 8 bank machines? | 15:37 |
| _florent_ | hmm, I have to check | 15:37 |
| _florent_ | I just made a simple change in the multiplexer to support 4 phases | 15:38 |
| lekernel | DDR3 has 8 banks (as opposed to 4 in DDR), so I would assume you ran into that | 15:38 |
| lekernel | are all 8 banks working, or are you just using 4? ;) | 15:38 |
| _florent_ | that what I have to check :) | 15:39 |
| _florent_ | at least I've changed ba width from 2 to 3 | 15:40 |
| lekernel | clock domain remapping in add_submodule does the remapping for the module and all its submodules, yes | 15:41 |
| _florent_ | ok thanks | 15:42 |
| lekernel | and btw you can use the shorter form: {"sys": foobar} => foobar | 15:42 |
| lekernel | sys is implied by default | 15:42 |
| lekernel | I wonder if ASMI can really meet timing when you have a lot of ports... I'm bumping into issues on the slowtan6 video mixer atm | 15:43 |
| _florent_ | for now my port won't run asmi at more than 50MHz, so it should be ok | 15:44 |
| lekernel | maybe I need to simplify the architecture a bit, eg just have a crossbar switch to the parallel bank machines | 15:44 |
| lekernel | this can also make it easier to have multiple memory controllers | 15:45 |
| _florent_ | what is the critical path on the asmi? | 15:45 |
| lekernel | the hub management | 15:46 |
| lekernel | so I want to replace that hub with a crossbar switch, and not have split transactions anymore | 15:46 |
| _florent_ | it can also interesting to have ports with integrated async fifo and / or bus width adaptation | 15:48 |
| lekernel | there can't be page hit optimization reordering anymore, too - only read/write turnaround minimization reordering, and parallel bank commands | 15:48 |
| lekernel | hmm, the problem is - how do you make that async fifo generic enough? | 15:49 |
| lekernel | how would you apply that to e.g. a framebuffer? | 15:49 |
| lekernel | run all the logic on the pixel clock? | 15:50 |
| lekernel | with just two async fifos into the system clock domain to send memory read commands and get the results? | 15:50 |
| _florent_ | the idea was just to be able to have ports with different frequency than the asmicon | 15:51 |
| _florent_ | instead of having the fifo in the framebuffer as it is now, having running @ pixel_clk | 15:52 |
| lekernel | different frequencies = more latency, more chances for non deterministic bugs that maximize time wastage, simulation difficulties that maximize time wastage even more | 15:53 |
| lekernel | and how does the framebuffer communicate with the cpu? | 15:54 |
| lekernel | to set scan address, video timing parameters, etc. | 15:54 |
| _florent_ | yes on this point you have to resynchronize all signals | 15:55 |
| lekernel | have some clock domain transfer support in csrgen? | 15:55 |
| _florent_ | why not ;) | 15:56 |
| lekernel | yeah, could work... | 15:57 |
| lekernel | but | 15:57 |
| lekernel | let's say we want 1080p | 15:57 |
| lekernel | then we have to run relatively large amounts of logic at 148MHz, which is, as I know so well, a royal pain in slowtan6 | 15:57 |
| _florent_ | yes but the framebuffer is maybe not a good example for that | 15:58 |
| _florent_ | if you have 1 Asmicon + N totally independent cores that need memory accesses | 15:59 |
| lekernel | I'd try to run everything on one single clock. minimizes memory latency and headaches. | 16:00 |
| _florent_ | my idea was that it's easier a generic port that can run at the core frequency instead of doing all clock domain crossing directly into each core | 16:00 |
| lekernel | why do all those cores need different clock domains? | 16:01 |
| larsc | because they can ;) | 16:01 |
| _florent_ | ;) | 16:04 |
| _florent_ | Imagine you have video multiplexer, 2 SD inputs, 2 HD inputs, 2 SD outputs, 2 HD outputs, you want to be able to redirect each SD input to each SD output, same for HD, I find it easier to have async port than have to handle clk domain transfer in each port | 16:08 |
| _florent_ | but anyway, for now I only want to be able to run the CPU at more than 50 MHz | 16:08 |
| lekernel | I'd rather implement read/write leveling than waste time on hacking asynchronous ASMI ports | 16:09 |
| lekernel | WL should be easy if Xilinx got the calibrated IODELAYS right in the 7 series | 16:10 |
| lekernel | for RL you just need to use DQS for reading | 16:10 |
| lekernel | I recommend you do a small soft FIFO that can store two bursts (ie 16 bits deep) | 16:10 |
| lekernel | then for data recapture just read the FIFO with the worst-case delay | 16:11 |
| lekernel | (read in the system clock domain) | 16:11 |
| lekernel | there's only one annoying detail, you won't do a FIFO with DDR registers | 16:12 |
| lekernel | so you need a IDDR | 16:12 |
| lekernel | and the last data pair will get stuck in it | 16:12 |
| lekernel | to solve this I propose the controller issues one dummy reads whenever there is a "bubble" in the read flow, to make the DDR toggle DQS and clock the data out of the IDDR and into the FIFO | 16:13 |
| lekernel | the dummy read is easy, just repeat the last read command immediately - it's guaranteed to be a page hit that will produce a continued burst | 16:14 |
| _florent_ | ok thanks, I remember we discussed about that before, now that I have something working on board, it will be easier to work on it | 16:17 |
| lekernel | )=(//(! thunderstorm | 17:52 |
| lekernel | I have Pearson correlation coefficients of 0.56, 0.53 and 0.78 between wer0/wer1, wer1/wer2 and wer2/wer0 | 18:39 |
| lekernel | 7K samples | 18:41 |
| Alarm_ | I do not see Xiang fu on IRC and he does not respond by email? | 18:42 |
| larsc | lekernel: what are werX? | 18:43 |
| lekernel | number of noncontrol words with too many transitions received during the last 2**24 words | 18:44 |
| lekernel | X = channel number | 18:44 |
| larsc | ah | 18:44 |
| lekernel | could be clock skew/glitches/failure? | 18:44 |
| larsc | Alarm_: <@qi-bot> larsc, xiangfu (~xiangfu@123.113.243.136) was last seen quitting #qi-hardware 12 hours 54 minutes ago | 18:45 |
| lekernel | s/skew/jitter | 18:45 |
| Alarm_ | larsc: OK thanks | 18:47 |
| larsc | lekernel: so this means there is quite a bit of correlation, right? | 18:59 |
| lekernel | I'm not a statistics expert, but I'd think so | 19:00 |
| lekernel | lol: removing the DCM_CLKGEN, which supposedly provides better clock jitter tolerance than the PLL, results in WER=0 and no more picture noise | 19:48 |
| lekernel | guess I just have to sort out the memory speed issues now, and the video mixer will be perfect :) | 19:49 |
| wpwrak | just don't use anything xilinx recommend :) | 19:49 |
| wpwrak | regarding the correlation, we already know there's a strong long-term correlation (the temperature dependency) | 19:53 |
| lekernel | that was correlation between the error rates on each channel, which suggested a clock problem | 19:54 |
| lekernel | or some other source of noise that would affect them all at the same time | 19:54 |
| wpwrak | yes. the temperature issue showed that too (without explaining the underlying problem, though) | 19:56 |
| lekernel | oh, I can already do 720p at WER < 5 :) | 19:56 |
| lekernel | 1280x720 | 19:56 |
| lekernel | not bad for that add on board | 19:56 |
| wpwrak | add a negative DCM_CLKGEN and it'll be perfect ;-) | 19:56 |
| wpwrak | indeed. you're way above any frequency such a contraption can reasonably be expected to handle | 19:58 |
| lekernel | hmm, perhaps I can even have 1080p24 on the inputs - which is a HDMI standard - and 1080p60 at the output | 20:48 |
| lekernel | that's a bit more than 8Gbps memory bandwidth, challenging but maybe doable | 20:48 |
| lekernel | so I guess next step is to fix ASMI | 20:49 |
| lekernel | ah, no it's 12Gbps bandwidth. won't work :( | 20:50 |
| lekernel | maybe if I output 1080p30 or 24 - don't know if monitors accept it from VGA ... | 20:51 |
| mwalle | hi | 20:53 |
| lekernel | hi mwalle | 20:54 |
| --- Wed May 29 2013 | 00:00 | |
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