#milkymist IRC log for Sunday, 2013-05-19

Fallenouhi!09:57
Fallenoulekernel: you were talking about the Mixxeo board, right? who picked the slow flash? and the ftdi chip? (and who did the "bad design" for this board ?)09:59
lekernelno, it's another board for some physics experiment10:13
lekernelof course mixxeo will use the same FTDI connections as the M1 - I'm not looking for trouble :)10:14
lekernelthe board was already designed this way when I got it10:14
Fallenouoh ok10:25
Fallenoudoes someone have a flickernoise binary (latest version with MIDI USB support) that I can flash on my M1?10:26
FallenouI think the web storage of releases is down10:26
Fallenoubios and bitstream are easy for me to generate, flickernoise has tons of dependencies I would like to skip the big xiangfu script part :)10:28
lekernelweb storage isn't down... http://milkymist.org/updates/10:36
lekernelit's independent from sharism/qi-hw10:36
Fallenouoh, good!10:37
Fallenouso current should contain usb midi stuff?10:38
lekernelyeah... gateware in git also contains some usb fixes that are not in the binaries - if you need those10:40
Fallenouok I will generate the gateware myself and take the flickernoise from your link then10:41
Fallenouthanks!10:41
lekernelso rtems is even worse than ise? ;)10:41
GitHub3[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/EwprEA10:43
GitHub3milkymist-ng/master d487dc6 Sebastien Bourdeauducq: software: add nofloat libbase for size-optimized binaries10:43
Fallenouit's just that there is too much dependencies :p10:44
Fallenougenerating the bitstream is just "make bitstream" and you're done10:44
Fallenou(ok it's long)10:45
wpwraklekernel: how sure are you of the clock-to-data synchronization ? i was thinking that, if we have a fairly regular pattern, perhaps an array of 1024 counters, indexed by the received pattern, could be used to gather statistics12:11
wpwrake.g., the all black pattern would have two high counts (for the "mostly high" and the "mostly low" pattern), plus a number of small counts, most of which would be the errors.12:12
wpwrakthat in turn should allow determining how the errors differ from the expected pattern12:13
lekernelhmm, that's an idea12:13
wpwrake.g., whether it's a shift of the whole pattern, whether one bit moved, etc.12:13
larscgood idea12:14
lekernela bit tricky to implement since you need BRAM and then do 1 read + 1 write at different addresses at every cycle12:14
lekernel(different addresses because the read will take one cycle)12:14
wpwrakhow many counters could you have without using difficult structures ?12:15
wpwraklet's say, 16 bit counters12:15
lekernelso you're using the two ports to do that, and then you also need read capability in the system clock domain12:15
lekernelalternatively, you could try reading using bitstream readback :)12:15
wpwrakthat's enough for about one second even when things are very very bad. 10 seconds or more if they're a bit more civilized12:16
lekernelassuming bitstream readback is a real third "hidden" port and won't do weird things if you access the BRAM from the design at the same time12:17
wpwrakwith < 1024 counters, you'd just hash or mask. as long as the data is more or less the same, you still get the same results. but it's of course more involved.12:17
wpwrakhmm, isn't "doing weird things" one of the mottoes of xilinx ? :)12:17
lekernelwhy not do that with the TFTP solution by the way?12:18
wpwrakyou mean retrieval ?12:19
lekerneluse the existing design that can send raw data from one channel to the computer with TFTP then do the processing with software12:19
wpwrakcould simply be keystroke, like 0 and 1. it's not as if you'd need to do this continuously12:20
wpwrakwell, maybe you do. but we'd find out about that when seeing the first results. if it's all noise, maybe it needs deeper analysis.12:20
wpwrakbut already 1 second should contain hundreds of error patterns12:21
larscyou could probably use two brams, use one to count the even words and one to count the odd ones and then just sum them up in sw12:22
lekernelwhy do you want to do this in gateware?12:22
wpwrakah yes, that would make it single-cycle12:22
lekernelwhat's wrong with sending the frames with TFTP?12:22
wpwrakah, i see. you'd record to DRAM.12:23
wpwrakand then send the buffer. yes. that's an option.12:23
lekernelit's not all noise btw - http://milkymist.org/dvi_working.png was recovered via raw TFTP data + processing in python12:23
wpwrakpretty neat12:23
lekernelof course, it looks suspiciously free of errors12:23
lekernelthat was without the 24 ohm resistors12:24
wpwrakoh, wow12:24
wpwrakthat's suspicious indeed12:24
lekernelhttps://github.com/sbourdeauducq/dvidebug12:24
lekerneluse with this core https://github.com/milkymist/milkymist-ng/blob/master/milkymist/dvisampler/debug.py12:25
lekernelwith a single ASMI port with 3 slots, and run the SoC at 83MHz again12:25
lekernelor maybe not that suspicious since I sometimes get WER = 012:26
lekernelover 600ms12:26
lekerneland that's only less than 3 frames, less than 50ms12:27
wpwrak(WER = 0 for a while) ah, interesting. so it's very bursty.12:27
lekernelthe WER counter resets every 2**24 words which is about 600ms with a 25MHz pixel clock12:28
Fallenouwhat's the prefered way of installing python3.3 on Ubuntu (which already has python3.2)? compiling the python3.3 from sources?12:28
lekerneland you actually get lots of zeros or values under 5, at least with the resistors12:28
wpwraki suppose the capture could also be extended to capture more data. maybe 64 MB. that should be ...58 frames (assuming each pixel occupies 30 bits)12:29
lekernelit's only one channel12:30
wpwrakah yes, silly me12:30
lekerneleach pixel is 10 bits + 6 bits of padding to align them to byte boundaries12:30
wpwrak116 frames then. more than a second :)12:30
lekernelyou should try running the current dvidebug stuff first12:31
lekernelI have changed things in the core and haven't tested it for a while12:31
wpwraksound good. but first, breakfast with a lot of coffee :)12:38
Fallenoulekernel: when you write (lambda a: a[27:29] == 3, self.wishbone2csr.wishbone) < it means bits [29:27] (in verilog syntax) of transaction address are 3'b011 ??13:27
Fallenouwhich would mean then ... 0x1800 0000 ??13:28
Fallenouwpwrak: what's the range() operator doing when applied to a fader in FPN again?13:30
FallenouI mean, what's the difference between fader1 and range(fader1)13:31
wpwrakfader1 = fader(...)  gets you the fader device14:05
wpwrakvar = range(fader1)  defines how the device's values are interpreted14:06
Fallenouok, I've done so far things like fader1 = fader(1, 0)14:06
wpwraksee also: cd flickernoise/src/compiler/doc && make && make again && xpdf midi.pdf14:06
Fallenouoh ok :)14:07
wpwrak(i had to look it up myself - been a long time ;-)14:07
Fallenouhehe14:07
Fallenouarg flash and ram have shared address bus on the Nexys3 board14:08
wpwrakbasically foo = fader(...) or such maps control elements to functions. and bar = range(...) binds those functions to variables14:08
Fallenouthat will lead to poor mibuild device file :/14:08
wpwrakdoes mibuild/migen even support bus sharing ? :)14:08
FallenouI will implement it inside the "submodule"14:09
FallenouI will call the block "Memory" and then do the differenciation ram/flash inside the Memory submodule14:09
Fallenouso all flash/ram pads will be "Memory" pads14:09
larscwpwrak: well internally it is all connected to the same bus anyway14:22
Fallenouwpwrak: does the below(var, value) still work?15:17
Fallenouparser says there is an error over there: http://www.milkymist.org/updates/current/patches/Rozzor%20&%20Aderrasi%20-%20Canon%20%28DMX%20out%29.fnp15:17
Fallenou5 lines from the bottom of the file15:17
Fallenouper_frame=warp = warp + if (below(kick,0), 0.5*treb, 0);15:17
wpwrakthe below ought to work, yes15:30
Fallenouhum ok15:31
FallenouI don't get how to send commands to the Micron np8p128a13t1760e flash15:31
Fallenouthere are addr[] data[] buses, we, ce, oe etc but I don't see any "control" bus15:32
Fallenouand the datasheet gives a list of "commands"15:32
Fallenouhow the hell do I send any command?15:32
wpwrakFallenou: all regression tests pass, so below() works :)15:37
wpwrakthe regression tests also check the patches15:37
GitHub196[flickernoise] wpwrak pushed 1 new commit to master: http://git.io/xX7I_w15:40
GitHub196flickernoise/master 3c4e04f Werner Almesberger: test/fold: fix "nothign" typos15:40
wpwraknow it's perfect :)15:41
Fallenou:p15:41
Fallenouok thanks15:41
lekernelFallenou, upper bound is exclusive so it's bits 27 and 2816:00
lekerneland the address (a signal) is in 32 bit words16:00
lekernelso the first address to match becomes 0x60000000 in bytes16:00
lekernelwpwrak, all bus sharing needs a special core, no matter which language they are written in. then you'd have that special "bus shared" interface in the mibuild description.16:02
wpwrakthat's roughly how i imagined it. sharing rarely comes for free :)16:03
Fallenouok so it's bits 29 and 30 for CPU access (byte access)16:03
Action: Fallenou is having troubles with PLL_ADV stuff for Nexys3 since clk is 100 MHz instead of 50 MHz on that board16:04
lekernelFallenou, you should make a combined flash/psram core16:04
Fallenousomething is wrong in the dynamic calculous16:04
Fallenoulekernel: yes that's what I thought16:04
lekernelI suppose the controls are similar16:04
lekernelthen you just assert the proper chip enable depending on one address bit16:05
Fallenouyes16:05
Fallenouhttp://pastebin.com/fawiuwyC ISE complaining16:06
Action: Fallenou checks in m1crg.v16:07
lekernelinteresting that you need to login for the flash errata but not the datasheet16:07
Fallenouyes =)16:08
Fallenouthey want to hide their errors16:08
lekernelit's not even technically flash16:08
lekernelhttp://en.wikipedia.org/wiki/Phase-change_memory16:08
Fallenouin the datasheet they don't say when the address is latched for a READ they only say it for a write16:09
lekernelit could be asynchronous access?16:09
lekernellike NOR?16:09
Fallenouhum maybe16:09
lekernelTo perform a READ operation, RST# and WE# must be de-asserted while CE# and OE#16:10
lekernelare asserted. CE# is the device select control. When asserted, it enables the Flash16:10
lekernelmemory device. OE# is the data output control. When asserted, the addressed Flash16:10
lekernelmemory data is driven onto the I/O bus.16:10
lekernelthat's all16:10
lekerneljust be wary of the 135ns address-to-data delay16:10
larscFallenou: what's the output frequency?16:10
FallenouI think I need to change in m1crg.v the 4*f_mult and 4*f_div by 2*f_mult and 2*f_div16:11
Fallenouyes it works, bitstream is now generated :)16:11
Fallenousomehow the PLL_ADV seems to multiply the input clock internally and then divide it for the output16:12
lekernelyou can try to boot the board with just the flash to start with16:12
Fallenouit was too much multiplied at the entry I guess so that the internal oscillator of the PLL could not survive such a frequency16:12
lekernelsee if you get any serial output and BIOS prompt16:12
lekernelthen add the PSRAM16:12
lekernelall you need is read only flash which is trivial... just take the existing norflash core16:12
Fallenouyes read only flash16:13
Fallenou18:10 < lekernel> just be wary of the 135ns address-to-data delay < IIUC I need to wait for OE# (what's the # for? negation ?) and that's all, right?16:14
Fallenoubefore latching the data_out16:14
lekernel"Leon Chua, who is considered to be the father of non-linear circuit theory, has argued that all 2-terminal non-volatile memory devices including phase change memory should be considered memristors."16:14
lekernelah, those self-serving wikipedia edits ... :-)16:15
Fallenou=)16:15
lekernelif you're just reading, hold OE# constant16:16
lekernel# is negation yes16:16
FallenouI don't understand the norFlash python file at all :o16:16
lekerneland just wait for a couple cycles after the address is changed16:16
Fallenouthe timeline stuff and the rd_timing16:16
lekernelit's simple - address and data of wb are sent to the flash, all the time16:17
Fallenouof 12 is the rd_timing it seems16:17
Fallenou-of+oh16:18
lekernelwhen a wb request arrives, you need to wait rd_timing cycles for the "wb address -> flash address pins -> flash read delay -> flash data pins -> wb data" process to complete16:18
lekernelso you ack the wb request with delay16:18
lekernelI think you can probably take the norflash core as-is, maybe adjust rd_timing and a couple details, and it would work16:19
Fallenouos timeline() is a tool to be able to act upon a start event (strobe+cyc) and then do stuff after x sys_clk cycles and then y sys_clk cycles etc ?16:20
Fallenou-os+so16:20
lekernelI like how Micron always says "Easy BGA" instead of "BGA"16:22
lekernelalmost sounds orwellian16:22
Fallenoulol16:22
FallenouFast Spartan6 (Fastan 6 ?)16:23
Fallenouwin 1816:35
lekernelwow, Chua's paper is so full of academic BS. I'm glad I don't have a PhD.16:40
lekernel"the periodic table of circuit elements" lol16:41
Fallenouoh, original norflash was already 16 bits access16:50
Fallenounice16:50
Fallenoulekernel: in m1's mibuild "python style" ucf file, the pads for flash addr and flash data, are they from MSB to LSB or the other way round ?16:51
lekernelfirst one is lsb16:52
Fallenouarg :(16:52
FallenouI've put MSB first, damn it16:52
Fallenouhave to rewrite all the pads :)16:52
Fallenouor change the order of the Cat( ) in norFlash/__init__.py maybe ...16:53
lekernelbetter do it cleanly and invert that list16:56
lekerneland heh16:56
lekernelit's python :)16:56
lekernell = [those pads you have written]16:56
lekernelprint(list(reversed(l))) and you're done16:56
lekernelwith just a bit of copy paste16:57
Fallenouyes I just did that with a python cmdline :)16:59
Fallenouhum I think I forgot to clock the flash17:02
Fallenouit seems the flash clk is directly hooked to one of the FPGA IO17:02
lekernelthere is no clock17:07
lekernelexcept for spi which you don't use17:07
Fallenouok17:10
lekernelwould be cool to parameterize lm32 with verilog parameters instead of that messy and non-reentrant include17:25
GitHub44[milkymist-ng] sbourdeauducq pushed 1 new commit to master: http://git.io/IbCjOQ17:46
GitHub44milkymist-ng/master 3eb41f7 Sebastien Bourdeauducq: Simplify system ID17:46
Fallenouantgreen: how do you write your code to Nexys3 Flash? You have some kind of "FPGA<->Flash" bridge? (like fjmem.bit)17:48
Fallenouor do you still use an embedded ROM?17:49
antgreenFallenou: I don't yet.  The only external memory I'm using is the pseudo-static RAM device17:49
antgreen(16M).17:49
antgreenYes, also embedded memory17:50
antgreenROM & RAM17:50
antgreenI  have my initial bootloader in embedded memory17:50
Fallenouoh, ok17:50
antgreenit downloads srec programs into psram and executes from there17:50
Fallenoudo you know if there is any easy way to write something to Flash?17:50
Fallenouany tool? something?17:50
antgreenonly on windows :-(17:51
Fallenouoh17:51
FallenouThe Flash chip does not even seem to be on the JTAG chain :o17:51
antgreenif I had a flash controller, then I could create one easily17:51
antgreenthat would be a good next project17:51
antgreenI'm leaving on a 4 day trip business tomorrow, and always get lots done then17:52
antgreenmaybe I'll try it.17:52
antgreenhttp://electronics.stackexchange.com/questions/34807/accesing-the-pcm-flash-memory-on-a-nexys-3-board17:54
lekernelFallenou, you can put the BIOS in BRAM17:54
lekernelfits in less than 16K if you trim it down17:54
antgreenyes, that's where my bootloader lives17:54
antgreenand it runs in BRAM RAM as well17:54
antgreenhehe - that stack exchange question was asked by a moxie user17:55
antgreendoes the lm32 have a bus watchdog, or something that looks for unmapped memory accesses?17:56
lekernelthere is an exception vector for when the wb error signal is asserted18:01
Fallenou19:54 < lekernel> Fallenou, you can put the BIOS in BRAM < yes, I think I will do that for now to validate the rest of the soc18:20
Fallenoubut then I will really need to put a program in flash :)18:20
lekernelno, you sfl-boot or net-boot directly to PSRAM18:21
lekerneland completely ignore the flash18:21
Fallenouoh, why not yes18:23
Fallenouhaving the bios download application to RAM18:23
Fallenouand put the bios in ROM18:23
GitHub198[mibuild] sbourdeauducq pushed 1 new commit to master: http://git.io/0pEemQ18:26
GitHub198mibuild/master e272e68 Sebastien Bourdeauducq: platforms/papilio_pro: swap tx/rx to be consistent with M118:26
antgreenwhat is sfl-boot?18:37
antgreenoh, serial line18:39
GitHub0[migen] sbourdeauducq pushed 2 new commits to master: http://git.io/woQIkQ18:56
GitHub0migen/master 7ada015 Sebastien Bourdeauducq: bus/csr/SRAM: support init18:56
GitHub0migen/master 5208baa Sebastien Bourdeauducq: bus/wishbone/SRAM: support init and read_only18:56
wpwrakhmm .. is the infrastructure for the dvidumper even around anymore ? the dma controls have changed completely and as far as i can tell, dvisampler now stores pixels, not raw patterns19:00
wpwrak"self.submodules.dma = spi.DMAWriteController(" hmm .. SPI ? wow19:03
lekernelsimple processor interface19:47
lekerneland yes19:47
lekernelthe infrastructure is still there; dvisampler stores pixels and that's why there's a separate "debug" core that stores raw19:48
lekernelftdi_eeprom won't even compile... yes, libftdi "is easy to use" and "works perfectly" - I see ...19:50
wpwrakah ! that's where it went. thanks !19:50
wpwrakthere are lies, damn lies, and then there's marketing :)19:50
lekernelcmake even produces a blank makefile, lol19:50
wpwrakcrapmake ? :)19:51
lekernel./ftdi_eeprom --read-eeprom conf.conf19:58
lekernelWarning: Not writing eeprom, you must supply a valid filename19:58
lekernelahem19:58
lekerneldid a Xilinx engineer write this?19:59
larscwell better than if it actually did write the eeprom20:00
lekernel?! the poor shit has a read eeprom mode, but then you can't rewrite the backup file you just made?20:16
lekerneloh my ...20:17
lekerneleeprom_set_value(ftdi, VENDOR_ID, cfg_getint(cfg, "vendor_id"));20:18
lekernel...20:18
lekernel    eeprom_set_value(ftdi, CHANNEL_A_DRIVER, DRIVER_VCP);20:18
lekernel    eeprom_set_value(ftdi, CHANNEL_B_DRIVER, DRIVER_VCP);20:18
lekernel    eeprom_set_value(ftdi, CHANNEL_C_DRIVER, DRIVER_VCP);20:18
lekernel    eeprom_set_value(ftdi, CHANNEL_D_DRIVER, DRIVER_VCP);20:18
lekernelahem ....20:19
lekernelgreat error reporting, too http://pastebin.com/KbQwh3Lz20:25
wpwrakdon't worry, there's a lot more badness where that came from :)20:38
lekernelftdi stuff is like raspberry pi, two devices with a large open source-ish community and no one to get things right20:42
wpwrakin many "communities" there's sub-"community" of "makers" and one of "followers". sometimes, there's hardly a difference between them. in other cases, there's a rather sharp divide.20:52
lekernelfinally found the right options, but for some reason the it would only write the first 128 bytes of the 256 from my backup ....20:55
wpwrakgee, so many surprises :)20:57
wpwrakdon't worry, the writes that go slightly wrong will only change undocumented bits that completely alter the function of the device20:57
wpwrakthis is kinda fun :) in an iain banks, the wasp factory kind of way. well, from the perspective of the one watching the wasp struggle towards the inevitable, of course.21:05
lekernelindeed, when you erase the eeprom and then attempt to flash it from a backup file, it reads a word from the eeprom that was just erased to determine its size21:06
lekernelvery clever :)21:07
wpwrakdon't worry, that's just a minor detour. you'll get back to the real road to hell quickly enough.21:13
lekernelah, you are right21:18
lekernelthough it was just ftdi_set_eeprom_buf() ignoring its size parameters. finally got my original backup written correctly.21:24
lekernelthe amount of bugs in ftdi chips and libftdi is quite impressive21:25
davidc__use the windows tool - I hate to say it but, libftdi / the ftdi_eeprom tool is completely fucking broken22:05
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